Qui V Nguyen

US Patent:

7586362, Sep 8, 2009

Filed:

Dec 12, 2007

Appl. No.:

11/955221

Inventors:

Feng Pan - Fremont CA, US
Jonathan H. Huynh - San Jose CA, US
Qui Vi Nguyen - San Jose CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G05F 1/01

US Classification:

327537, 327536

Abstract:

Techniques of providing a low output voltage, high current capability charge pump are given. The charge pump has multiple capacitors along with switching circuitry. In an initialization phase, the first plate of each of the capacitors is connected to receive a regulator voltage and the second plate of each capacitor is connected to ground. In a transfer phase, the capacitors are connected in series, where, for each capacitor after the first, the second plate is connected to the first plate of the preceding capacitor in the series. The output voltage of the pump is from the first plate of the last capacitor in the series. Regulation circuitry generates the regulator voltage from a reference voltage to have a value responsive to the output voltage level of the pump.

US Patent:

7683700, Mar 23, 2010

Filed:

Jun 25, 2008

Appl. No.:

12/146243

Inventors:

Jonathan H. Huynh - San Jose CA, US
Qui Vi Nguyen - San Jose CA, US
Feng Pang - Fremont CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G05F 1/10

US Classification:

327536

Abstract:

A charge pump system for supplying an output voltage to a load is described. It includes a regulation circuit connected to receive the output voltage and derive an enable signal from it and multiple charge pump circuits connected in parallel to supply the output voltage. Each of the charge pump circuits is also connected to receive a clock signal and the enable signal. The system also includes one or more delay circuit elements, where a corresponding one or more, but less than all, of the charge pump circuits are connectable to receive the enable signal delayed by the corresponding delay circuit element.

US Patent:

8004917, Aug 23, 2011

Filed:

Sep 22, 2008

Appl. No.:

12/235467

Inventors:

Feng Pan - Fremont CA, US
Yuxin Wang - Sunnyvale CA, US
Jonathan H. Huynh - San Jose CA, US
Albert Chang - Santa Clara CA, US
Khin Htoo - Sunnyvale CA, US
Qui Vi Nguyen - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 7/04

US Classification:

365211, 365212, 365214

Abstract:

A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the node supplies the reference voltage. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source.

US Patent:

8106701, Jan 31, 2012

Filed:

Sep 30, 2010

Appl. No.:

12/895457

Inventors:

Jonathan Hoang Huynh - San Jose CA, US
Feng Pan - Fremont CA, US
Qui Vi Nguyen - San Jose CA, US
Trung Pham - Fremont CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

H03L 5/00

US Classification:

327333, 326 62, 326 81

Abstract:

A level shifter circuit suitable for high voltage applications with shoot-through current isolation is presented. The level shifter receives a first enable signal and receives an input voltage at a first node and supplies an output voltage at a second node. The circuit provides the output voltage from the input voltage in response to the first enable signal being asserted and sets the output node to a low voltage value when the first enable signal is de-asserted. The level shifting circuit includes a depletion type NMOS transistor, having a gate connected to the output node, and a PMOS transistor, having a gate connected to the first enable signal. It also includes a first resistive element that is distinct from the NMOS and PMOS transistors. The NMOS transistor, the PMOS transistor and the first resistive elements are connected in series between the first and second nodes, with the NMOS transistor being connected to the first node. The level shifter further includes a discharge circuit connected to the second node and to receive a second enable signal.

US Patent:

8228739, Jul 24, 2012

Filed:

Jul 18, 2011

Appl. No.:

13/184778

Inventors:

Feng Pan - Fremont CA, US
Yuxin Wang - Sunnyvale CA, US
Jonathan H. Huynh - San Jose CA, US
Albert Chang - Santa Clara CA, US
Khin Htoo - Sunnyvale CA, US
Qui Vi Nguyen - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 11/34

US Classification:

36518521, 36518518, 365211, 365212

Abstract:

A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the reference voltage is provided from the node. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source.

US Patent:

8395434, Mar 12, 2013

Filed:

Oct 5, 2011

Appl. No.:

13/253784

Inventors:

Qui Vi Nguyen - San Jose CA, US
Takuya Ariki - Naka-ku, JP
Jongmin Park - Cupertino CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

H03L 5/00

US Classification:

327333, 326 63, 326 81

Abstract:

A level shifter circuit is presented that can apply a negative voltage level to non-selected blocks while still being able to drive a high positive level when selected. An exemplary embodiment presents a negative level shifter that is not susceptible to low voltage pfet breakdown. This allows for a high voltage level shifter (transfer gate) that can drive a negative level for unselected blocks and, when enabled for a selected block, can still drive a positive high voltage level. By using a pair of low voltage PMOS device whose n-wells share the same level as other PMOS transistors in the design, layout area can be minimized. The gates of this pair of PMOSs are connected to VSS, thereby preventing these low voltage PMOS devices from thin oxide breakdown.

US Patent:

8400212, Mar 19, 2013

Filed:

Sep 22, 2011

Appl. No.:

13/240623

Inventors:

Qui Vi Nguyen - San Jose CA, US
Trung Pham - Fremont CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G05F 1/10

US Classification:

327536

Abstract:

A regulator system for a charge pump system divides the binary decoding into two branches. One controls a set of parallel connected resistors for fine output voltage steps. The other branch controls a serial resistor to provide the large step size. For example, a 9-bit digital input signal is split into 2 least significant for the fine adjustment and the other 7 bits for the larger adjustments. In the example of a 50 mV step size, in one current path 2 bits of the binary input then control two parallel resistors for 50 mV and 100 mV step size, and in the other current path 7 bits are used for one-hot-decode control serial resistors to provide a 200 mV step size. A unity gain operational amplifier and a high voltage device are added in between the two branches to decouple the parasitic capacitance of large parallel resistors from the other elements.

US Patent:

8514628, Aug 20, 2013

Filed:

Sep 22, 2011

Appl. No.:

13/240664

Inventors:

Qui Vi Nguyen - San Jose CA, US
Khin Htoo - San Jose CA, US
Jonathan Huynh - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 11/34
G11C 16/04
G11C 7/00
G05F 1/10

US Classification:

36518518, 36518523, 36518907, 36518919

Abstract:

A charge pump system uses a dynamic switching approach, where the pump connections are independent of the load for each output. One large pump is designed to be shared between all of the outputs for use during the ramp up during recovery, with each output level also have one designated pump to maintain its level when under regulation. Each small pump is designed with capability that can maintain its output at its regulation level. Each of these pumps can be tailored to the corresponding output level, such as the number of stages being higher in the pump to supply the higher output level. The large pump unit is constructed to be ample to provide sufficient drive to be able to assist in the ramp up phase for all of the outputs and has as many switches needed to connect the pump with all the needed outputs.