Rahul S Gupta

US Patent:

7355718, Apr 8, 2008

Filed:

Apr 4, 2006

Appl. No.:

11/278559

Inventors:

William Jacob Craft - Whitsett NC, US
Rahul Gupta - Wilmington DE, US

Assignee:

North Carolina Agricultural and Technical State University - Greensboro NC

International Classification:

G01B 9/02
G01L 1/24

US Classification:

356480, 356 355, 356519

Abstract:

An interferometer pressure sensor includes a reflective film configured to change a position thereof responsive to a pressure change and an interferometer element configured to detect the position change of the reflective film. A holder is configured to hold the reflective film and the interferometer element. The holder includes a first member formed of a first material having a first coefficient of thermal expansion and a second member formed of a second material having a second coefficient of thermal expansion that is different from the first coefficient of thermal expansion. The first member and the second member of the holder are sized and configured based on the first coefficient of thermal expansion and the second coefficient of thermal expansion so that a distance between the reflective film and the interferometer element is substantially constant over a temperature range.

US Patent:

7868426, Jan 11, 2011

Filed:

Jul 28, 2008

Appl. No.:

12/180848

Inventors:

Brian G. Willis - Wilmington DE, US
Rahul Gupta - Newark DE, US

Assignee:

University of Delaware - Newark DE

International Classification:

H01L 29/06
H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257618, 257343, 257377, 257382, 257E2907, 977707, 977762

Abstract:

A monolithic pair of nanoscale probes, including: a substrate having a cavity that extends from a surface of the substrate into its body; a dielectric layer formed on the substrate; a pair of nanoscale probe precursors formed over the dielectric layer; a plurality of sub-monolayers of electrode material selectively atomic layer deposited over the pair of nanoscale probe precursors. The dielectric layer includes a window that extends through it to the cavity of the substrate such that a portion of the dielectric layer adjacent to the window extends over the cavity. The pair of nanoscale probe precursors includes a pair of edges facing each other across the window. These edges correspond to tips of the pair of nanoscale probes. The sub-monolayers of electrode material include the pair of edges, so that a distance between the tips of the nanoscale probes is between about 0. 1 nm and about 20 nm.

US Patent:

20110283873, Nov 24, 2011

Filed:

Jul 31, 2008

Appl. No.:

12/673418

Inventors:

Haydn N.G. Wadley - Keswick VA, US
Yellapu V. Murty - Charlottesville VA, US
Tyrone Jones - Bel Air MD, US
Rahul Gupta - Wilmington DE, US
Matthew Burkins - Forest Hill MD, US

Assignee:

UNIVERSITY OF VIRGINIA PATENT FOUNDATION - Charlottesville VA
DEPARTMENT OF THE ARMY - Adelphi MD
CELLULAR MATERIALS INTERNATIONAL, INC. - Charlottesville VA

International Classification:

F41H 5/04
B63B 3/10
B64G 1/52
B64D 45/00
B61D 17/00
F41H 7/02
F41H 5/24

US Classification:

89 3602, 89904, 89914, 89915, 89910, 89917, 89930, 89920

Abstract:

Structures based upon periodic cellular materials that provide a potential for defeating combinations of both air blast loading and ballistic attack either sequentially or simultaneously, or combination of both. The cellular structures may also be configured to meet the stiffness and strength support requirements of particular vehicle or other applications, systems or structures. The armor is therefore potentially able to support normal service loads and defeat blast and ballistic threats when necessary. The structure provides for using efficient load support capabilities of the material (without a high armor protection level) in low threat conditions, as well as the ability to modify the system to increase its level protection to a desired or required level. This would reduce the weight of the protection system in normal (low threat) conditions which reduces vehicle wear and tear, as well as cost savings in fabrication of applicable structures or systems.

US Patent:

20120227762, Sep 13, 2012

Filed:

Oct 14, 2010

Appl. No.:

13/502057

Inventors:

Christian Dussarrat - Wilmington DE, US
Rahul Gupta - Newark DE, US
Vincent M. Omarjee - Grenoble, FR
Nathan Stafford - Damascus OR, US

Assignee:

American Air Liquide, Inc. - Fremont CA

International Classification:

B08B 7/00

US Classification:

134 11

Abstract:

Disclosed are compounds for plasma ashing photoresist layers on a substrate and methods of using the same. The plasma ashing compounds induce limited to no damage to the underlying layer, such as the low-k film layer.

US Patent:

59056380, May 18, 1999

Filed:

Dec 18, 1997

Appl. No.:

8/993815

Inventors:

James D. MacDonald - Apex NC
Walter M. Marcinkiewicz - Apex NC
Rahul Gupta - Cary NC

Assignee:

Ericsson Inc. - Research Triangle Park NC

International Classification:

H05K7/10;7/12

US Classification:

361769

Abstract:

An apparatus and method for packaging a microelectronic device to be connectable to a distribution circuit. The apparatus is in the form of a microelectronic package including a microelectronic device having first and second oppositely facing surfaces and a plurality of Input/Output pads on the first surface capable of being electrically interconnected to a distribution circuit, a base adapted to support the microelectronic device in a predetermined operative relationship to a distribution circuit, and a first layer of elastomer gel sandwiched between the first surface and the base. The first surface of the microelectronic device overlays the base so as to allow an electrical interconnection through the base between the microelectronic device and a distribution circuit.

US Patent:

59148640, Jun 22, 1999

Filed:

Dec 22, 1997

Appl. No.:

8/995388

Inventors:

James D. MacDonald - Apex NC
Walter M. Marcinkiewicz - Apex NC
Rahul Gupta - Cary NC

Assignee:

Ericsson Inc. - Research Triangle Park NC

International Classification:

H05K 702
F16M 1300

US Classification:

361752

Abstract:

A shock and vibration attenuating structure and method is provided for an electronic assembly including a distribution circuit and at least one electronic component mounted on a surface of the distribution circuit. The shock and vibration attenuating structure includes a layer of elastomer material adapted to overlay the distribution circuit and substantially conform to the at least one electronic component. The layer includes a negative image of at least part of the at least one electronic component to allow the elastomer material to envelope the at least part of the at least one electronic component, and at least one relief formed in the elastomer material. The at least one relief is spaced from the negative image of the at least one electronic component and has a predetermined size, shape, and location in the elastomer material selected to protect the electronic component from shock and vibration induced loads and deflections with the layer overlaying the electronic assembly.

US Patent:

61845701, Feb 6, 2001

Filed:

Oct 28, 1999

Appl. No.:

9/428861

Inventors:

James D. MacDonald - Apex NC
Rahul Gupta - Apex NC

Assignee:

Ericsson Inc. - Research Triangle Park NC

International Classification:

H01L 2906

US Classification:

257622

Abstract:

An integrated circuit includes an integrated circuit die having first and second opposing faces, a plurality of spaced apart bonding regions on the first face, and at least one groove in the second face. The at least one groove allows the die to flex upon application of stress to the bonding regions due to thermal cycling of the integrated circuit die, compared to absence of the at least one groove. Preferably, multiple grooves are provided, a respective one of which extends between a respective pair of adjacent spaced apart bonding regions. The grooves may be fabricated by sawing and/or etching the grooves in the second face. The sawing and/or etching may be performed at the wafer stage, before the integrated circuit dies are singulated. Alternatively, the sawing and/or etching may take place after the integrated circuit dies are singulated from the wafer.

US Patent:

20210369169, Dec 2, 2021

Filed:

Aug 4, 2021

Appl. No.:

17/394355

Inventors:

- Minneapolis MN, US
Jianping Wu - Chapel Hill NC, US
Rahul Gupta - Irvine CA, US
Yan Zhao - Enschede, NL

International Classification:

A61B 5/316
A61N 1/36
A61B 5/00
A61B 5/374

Abstract:

In some examples, a processor determines a patient state based on activity of a bioelectrical brain signal of a patient in one or more frequency sub-bands of a frequency band of interest. For example, a processor may determine a patient state based on the power level of a bioelectrical brain signal of the patient in one or more frequency sub-bands of a frequency band, or based on a spectral pattern of a bioelectrical brain signal in a frequency band, such as a shift in a power distribution between sub-bands, a change in the peak frequency within one or more sub-bands, a pattern of the power distribution over one or more frequency sub-bands, or a width or a variability of one or more sub-bands exhibiting a relatively high or low level of activity.