Rajat Dhawan

US Patent:

7212631, May 1, 2007

Filed:

Aug 1, 2001

Appl. No.:

09/920784

Inventors:

Roberto Fabian Averbuj - San Diego CA, US
Pradeep Kumar Mishra - San Diego CA, US
Rajat Rajinderkumar Dhawan - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H04L 9/00

US Classification:

380 37, 380259, 380 44

Abstract:

Techniques for efficient KASUMI ciphering are disclosed. In one aspect, one KASUMI round for generating a fractional portion of the KASUMI cipher is deployed with appropriate feedback such that eight sequential rounds produce the KASUMI output. In another aspect, one third of the FO function is deployed with appropriate feedback such that three successive cycles produce the FO output. In yet another aspect, the FI function is deployed with appropriate feedback such that two subsequent cycles produce the FI output. In yet another aspect, a sub-key generator comprising two shift registers produces sub-keys for each round and sub-stage thereof in an efficient manner. These aspects, collectively, yield the advanced benefits of low area and low cost implementations of KASUMI with a simple user interface. Various other aspects of the invention are also presented.

US Patent:

8089486, Jan 3, 2012

Filed:

Mar 21, 2005

Appl. No.:

11/086474

Inventors:

Michael Hugh Anderson - Leucadia CA, US
Dan Minglun Chuang - San Diego CA, US
Geoffrey Shippee - Palo Alto CA, US
Rajat Rajinderkumar Dhawan - San Diego CA, US
Chun Yu - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06T 1/20

US Classification:

345506

Abstract:

A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.

US Patent:

20030031158, Feb 13, 2003

Filed:

May 31, 2001

Appl. No.:

09/871563

Inventors:

Nitin Kasturi - Los Gatos CA, US
Rajat Dhawan - San Diego CA, US
Daisuke Terasawa - San Diego CA, US
Avneesh Agrawal - San Jose CA, US
Arak Sutivong - Stanford CA, US

International Classification:

H04B007/216

US Classification:

370/342000, 370/441000

Abstract:

Techniques for efficient W-CDMA modulation are disclosed. In one aspect, a multiplexing/coding chain for use in modulation such as that defined by the W-CDMA specification is disclosed. In another aspect, transport blocks are processed and concatenated, utilizing memory efficiently. This aspect has the further benefit of preparing transport channels for efficient subsequent processing. It also allows for ease of interface with the transport channel source. In another aspect, the use of repeated channel coding is used in lieu of an interleaver memory to provide channel coding and interleaving. These aspects, collectively, yield the advanced benefits of a system, such as W-CDMA, in a hardware efficient manner. The techniques described herein apply equally to both access points and access terminals. The techniques are not limited to W-CDMA systems; they are quite suitable to other systems requiring the various benefits the invention offers. Various other aspects of the invention are also presented.

US Patent:

20030065697, Apr 3, 2003

Filed:

Oct 17, 2001

Appl. No.:

09/981130

Inventors:

Shimman Patel - San Diego CA, US
Andrew Kan - San Diego CA, US
Rajat Dhawan - San Diego CA, US

International Classification:

G06F007/38

US Classification:

708/491000

Abstract:

A fast, iterative techique for evaluating M modulo J which may be easily implemented in hardware. In the illustrative embodiment, the invention includes a first circuit () for decomposing M into two integers A and B=M-A; a second circuit () for evaluating (A modulo J); a third circuit () for evaluating M′=(A modulo J)+B; and, a fourth circuit () for determining whether to output M′ as the final answer, or to feedback M′ to said first means to evaluate M′ modulo J.

US Patent:

20110276747, Nov 10, 2011

Filed:

May 5, 2011

Appl. No.:

13/101947

Inventors:

Robert Jason Fuchs - San Diego CA, US
Michael A. Kongelf - San Diego CA, US
Christian O. Thelen - San Diego CA, US
Rajat R. Dhawan - San Diego CA, US
Hao Xu - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 12/00
G06F 12/02

US Classification:

711103, 711154, 711E12002, 711E12008

Abstract:

Certain aspects of the present disclosure relate to a method and apparatus for processing wireless communications. According to certain aspects, a linked list of chunks of memory used to store logarithmic likelihood ratio (LLR) values for a transport block is generated. Each chunk holds LLR values for a code block of the transport block. The linked list is then provided to a hardware circuit for traversal. According to certain aspects, the hardware circuit may be an application specific integrated circuit (ASIC) processor or field programmable gate array (FPGA) configured to traverse the linked list of chunks of memory used to store LLR values.