Intel Corporation May 1984 - May 2016
Principal Engineer
Phoenix Arizona Area May 1984 - May 2016
Education:
Lehigh University 1982 - 1986
Doctorates, Doctor of Philosophy, Materials Science, Philosophy
Indian Institute of Technology, Madras
Bachelors, Metallurgical Engineering
Skills:
Ic Engineering Management Failure Analysis Spc Asic Characterization Thin Films Design of Experiments Semiconductors Semiconductor Industry Vlsi Silicon R&D Cmos Soc Materials Science
Us Patents
Backside Metallization On Sides Of Microelectronic Dice For Effective Thermal Contact With Heat Dissipation Devices
Rajen Dias - Phoenix AZ Biju Chandran - Chandler AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23544
US Classification:
257620, 257712
Abstract:
A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a trench sidewall, a lip and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the trench sidewall.
Flip-Chip Device With Multi-Layered Underfill Having Graded Coefficient Of Thermal Expansion
A die with flip chip bumps including at least one layer of filled underfill on the die surface and a layer of unfilled underfill over the filled underfill and the flip chip bumps. An IC assembly including a substrate with bumps and at least one layer of filled underfill on the substrate surface and a layer of unfilled underfill over the filled underfill and the bumps. A die or IC assembly with a plurality of filled underfill layers with differing CTE. Methods of making the dies and IC assemblies.
A die with flip chip bumps including at least one layer of filled underfill on the die surface and a layer of unfilled underfill over the filled underfill and the flip chip bumps. An IC assembly including a substrate with bumps and at least one layer of filled underfill on the substrate surface and a layer of unfilled underfill over the filled underfill and the bumps. A die or IC assembly with a plurality of filled underfill layers with differing CTE. Methods of making the dies and IC assemblies.
Backside Metallization On Microelectronic Dice Having Beveled Sides For Effective Thermal Contact With Heat Dissipation Devices
Rajen Dias - Phoenix AZ, US Biju Chandran - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L021/44 H01L021/48 H01L021/50
US Classification:
438121, 438122
Abstract:
A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a beveled sidewall and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the beveled sidewall.
Thermal Interface Apparatus, Systems, And Fabrication Methods
An apparatus and system, as well as fabrication methods therefor, may include a unitary, substantially uniformly distributed transfer material coupled to a carrier material.
Backside Metallization On Sides Of Microelectronic Dice For Effective Thermal Contact With Heat Dissipation Devices
Rajen Dias - Phoenix AZ, US Biju Chandran - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/48 H01L 21/44 H01L 21/50
US Classification:
438122, 438458, 438460
Abstract:
A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a trench sidewall, a lip and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the trench sidewall.
Rajen Dias - Phoenix AZ, US Biju Chandran - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/48
US Classification:
257786, 257773, 257782
Abstract:
A microelectronic assembly including a plurality of conductive columns extending from a bond pad of a microelectronic device and a conductive adhesive on a land pad of a carrier substrate electrically attached to the conductive columns.
A microelectronic assembly including a plurality of conductive columns extending from a bond pad of a microelectronic device and a conductive adhesive on a land pad of a carrier substrate electrically attached to the conductive columns.