Rajen C Dias

age ~68

from Phoenix, AZ

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Also known as:
  • Rajen M Dias
  • Rajen D Dias
  • Rajendra Cyprian Dias
  • Rajendra C Dias
  • Maryann Dias
  • Ryan Dias
Phone and address:
4134 Windsong Dr, Phoenix, AZ 85048
4807591121
Related to:
Connected to:

Rajen Dias Phones & Addresses

  • 4134 Windsong Dr, Phoenix, AZ 85048 • 4807591121
  • Alamogordo, NM
  • Tempe, AZ
  • Maricopa, AZ
  • 14230 S 14Th St, Phoenix, AZ 85048 • 4802359639

Work

  • Company:
    Intel corporation
    May 1984 to May 2016
  • Position:
    Principal engineer

Education

  • Degree:
    Doctorates, Doctor of Philosophy
  • School / High School:
    Lehigh University
    1982 to 1986
  • Specialities:
    Materials Science, Philosophy

Skills

Ic • Engineering Management • Failure Analysis • Spc • Asic • Characterization • Thin Films • Design of Experiments • Semiconductors • Semiconductor Industry • Vlsi • Silicon • R&D • Cmos • Soc • Materials Science

Industries

Semiconductors

Resumes

Rajen Dias Photo 1

Rajen Dias

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Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Intel Corporation May 1984 - May 2016
Principal Engineer
Phoenix Arizona Area May 1984 - May 2016
Education:
Lehigh University 1982 - 1986
Doctorates, Doctor of Philosophy, Materials Science, Philosophy Indian Institute of Technology, Madras
Bachelors, Metallurgical Engineering
Skills:
Ic
Engineering Management
Failure Analysis
Spc
Asic
Characterization
Thin Films
Design of Experiments
Semiconductors
Semiconductor Industry
Vlsi
Silicon
R&D
Cmos
Soc
Materials Science

Us Patents

  • Backside Metallization On Sides Of Microelectronic Dice For Effective Thermal Contact With Heat Dissipation Devices

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  • US Patent:
    6812548, Nov 2, 2004
  • Filed:
    Nov 30, 2001
  • Appl. No.:
    10/000229
  • Inventors:
    Rajen Dias - Phoenix AZ
    Biju Chandran - Chandler AZ
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 23544
  • US Classification:
    257620, 257712
  • Abstract:
    A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a trench sidewall, a lip and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the trench sidewall.

  • Flip-Chip Device With Multi-Layered Underfill Having Graded Coefficient Of Thermal Expansion

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  • US Patent:
    6815831, Nov 9, 2004
  • Filed:
    Dec 12, 2001
  • Appl. No.:
    10/012409
  • Inventors:
    Rajen C. Dias - Phoenix AZ
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 2348
  • US Classification:
    257778, 257789, 257790, 257737, 257738
  • Abstract:
    A die with flip chip bumps including at least one layer of filled underfill on the die surface and a layer of unfilled underfill over the filled underfill and the flip chip bumps. An IC assembly including a substrate with bumps and at least one layer of filled underfill on the substrate surface and a layer of unfilled underfill over the filled underfill and the bumps. A die or IC assembly with a plurality of filled underfill layers with differing CTE. Methods of making the dies and IC assemblies.

  • Flip Chip Underfill Process

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  • US Patent:
    6861285, Mar 1, 2005
  • Filed:
    Apr 4, 2003
  • Appl. No.:
    10/407534
  • Inventors:
    Rajen C. Dias - Phoenix AZ, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L021/44
  • US Classification:
    438108, 438118, 438613
  • Abstract:
    A die with flip chip bumps including at least one layer of filled underfill on the die surface and a layer of unfilled underfill over the filled underfill and the flip chip bumps. An IC assembly including a substrate with bumps and at least one layer of filled underfill on the substrate surface and a layer of unfilled underfill over the filled underfill and the bumps. A die or IC assembly with a plurality of filled underfill layers with differing CTE. Methods of making the dies and IC assemblies.

  • Backside Metallization On Microelectronic Dice Having Beveled Sides For Effective Thermal Contact With Heat Dissipation Devices

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  • US Patent:
    6955947, Oct 18, 2005
  • Filed:
    Sep 14, 2004
  • Appl. No.:
    10/941185
  • Inventors:
    Rajen Dias - Phoenix AZ, US
    Biju Chandran - Chandler AZ, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L021/44
    H01L021/48
    H01L021/50
  • US Classification:
    438121, 438122
  • Abstract:
    A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a beveled sidewall and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the beveled sidewall.

  • Thermal Interface Apparatus, Systems, And Fabrication Methods

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  • US Patent:
    7042729, May 9, 2006
  • Filed:
    Jun 24, 2003
  • Appl. No.:
    10/608519
  • Inventors:
    Rajen C. Dias - Phoenix AZ, US
    Yongmei Liu - Gilbert AZ, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H05K 7/20
  • US Classification:
    361708, 165 802, 165185, 257707, 257713, 361707, 361710, 428 409
  • Abstract:
    An apparatus and system, as well as fabrication methods therefor, may include a unitary, substantially uniformly distributed transfer material coupled to a carrier material.

  • Backside Metallization On Sides Of Microelectronic Dice For Effective Thermal Contact With Heat Dissipation Devices

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  • US Patent:
    7064014, Jun 20, 2006
  • Filed:
    Aug 10, 2004
  • Appl. No.:
    10/916055
  • Inventors:
    Rajen Dias - Phoenix AZ, US
    Biju Chandran - Chandler AZ, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 21/48
    H01L 21/44
    H01L 21/50
  • US Classification:
    438122, 438458, 438460
  • Abstract:
    A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a trench sidewall, a lip and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the trench sidewall.

  • Microelectronic Device Interconnects

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  • US Patent:
    7078822, Jul 18, 2006
  • Filed:
    Jun 25, 2002
  • Appl. No.:
    10/183874
  • Inventors:
    Rajen Dias - Phoenix AZ, US
    Biju Chandran - Chandler AZ, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 23/48
  • US Classification:
    257786, 257773, 257782
  • Abstract:
    A microelectronic assembly including a plurality of conductive columns extending from a bond pad of a microelectronic device and a conductive adhesive on a land pad of a carrier substrate electrically attached to the conductive columns.

  • Microelectronic Device Interconnects

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  • US Patent:
    7314817, Jan 1, 2008
  • Filed:
    May 16, 2005
  • Appl. No.:
    11/131068
  • Inventors:
    Rajen Dias - Phoenix AZ, US
    Biju Chandran - Chandler AZ, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H01L 21/44
    H01L 23/52
    H01L 23/48
    H01L 29/40
    H01L 23/485
    H01L 23/488
  • US Classification:
    438612, 438613, 257739, 257778, 257E23021, 257E23023
  • Abstract:
    A microelectronic assembly including a plurality of conductive columns extending from a bond pad of a microelectronic device and a conductive adhesive on a land pad of a carrier substrate electrically attached to the conductive columns.

Mylife

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Rajen Dias Phoenix AZ

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Youtube

Indian Football Team ALL Goals Asia Cup 2011 HD

Indian Football Team ALL Goals Asia Cup 2011 HD

"Indian Football Team" india football "Asia Cup" 2011 goals "Sunil Chh...

  • Category:
    Sports
  • Uploaded:
    31 Jan, 2011
  • Duration:
    2m 50s
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