Rajendra N Gandhi

US Patent:

7398335, Jul 8, 2008

Filed:

Nov 22, 2004

Appl. No.:

10/994829

Inventors:

Bradley S. Sonksen - Margarita CA, US
Kuangfu D. Chu - Irvine CA, US
Rajendra R. Gandhi - Laguna Niguel CA, US

Assignee:

QLOGIC, Corporation - Aliso Viejo CA

International Classification:

G06F 13/00
G06F 15/16
G06F 13/28

US Classification:

710 35, 709232, 710 18, 710 22

Abstract:

Method and system for optimizing DMA request processing is provided. The system includes a HBA that uses a dynamic DMA maximum write burst count sizing to optimize processing of write and read requests, wherein the HBA includes a DMA optimizer module that selects a certain write burst size to adjust performance when read and write DMA requests are being utilized. The DMA optimizer module can toggle between write and read request priority based on a maximum write request burst size. A shorter maximum write burst size provides more opportunity to issue read requests and a larger maximum burst size provides a better write request performance. The method includes, evaluating a read request throughput rate; evaluating a write request throughput rate; evaluating a read request utilization rate; evaluating a write request utilization rate; and adjusting a maximum write burst size.

US Patent:

7577772, Aug 18, 2009

Filed:

Sep 8, 2004

Appl. No.:

10/935919

Inventors:

Bradley S. Sonksen - Rancho Santa Margarita CA, US
Kuangfu D. Chu - Irvine CA, US
Rajendra R. Gandhi - Laguna Niguel CA, US

Assignee:

QLOGIC, Corporation - Aliso Viejo CA

International Classification:

G06F 13/18
G06F 3/00

US Classification:

710 22, 710 5

Abstract:

A host bus adapter coupled to a network and a host computing system is provided. The host bus adapter includes a direct memory access (“DMA”)mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection module includes a DMA counter that counts a number of times a single DMA channel is exclusively serviced by the arbitration module and if the DMA counter value is equal to a threshold value, then the DMA mode detection module enables a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data. The single channel mode is enabled for a certain duration. The host bus adapter includes a rule based segmentation logic that may be enabled and/or disabled by host bus adapter firmware and/or detection of a single channel mode condition.

US Patent:

7577773, Aug 18, 2009

Filed:

Sep 9, 2005

Appl. No.:

11/222936

Inventors:

Rajendra R. Gandhi - Laguna Niguel CA, US
Kuangfu D. Chu - Irvine CA, US
Jerald K. Alston - Coto de Caza CA, US

Assignee:

QLOGIC, Corporation - Aliso Viejo CA

International Classification:

G06F 13/28

US Classification:

710 22, 718101

Abstract:

Method and system for processing read requests sent by a network interface device to a host system is provided. The method includes sending staggered read requests within a programmable time interval (“T”), wherein a transmit direct memory access (DMA) module sends more than one read request to the host system within the time interval T; placing data received from the host system in response to the read requests in independent slots of a transmit buffer; and unloading the transmit buffer slots based on an unload command, wherein the unload command is based on a mapping of read requests corresponding to transmit buffer slot locations where data from the host system is stored, and data is sent from the transmit buffer to a network device in the same order as the read requests that are sent from the network interface device to host system.

US Patent:

7594057, Sep 22, 2009

Filed:

Jan 9, 2006

Appl. No.:

11/328358

Inventors:

Rajendra R. Gandhi - Laguna Niguel CA, US
Kuangfu D. Chu - Irvine CA, US

Assignee:

QLOGIC, Corporation - Aliso Viejo CA

International Classification:

G06F 13/36

US Classification:

710308, 710 22, 710 33, 710 39, 710 54, 710310

Abstract:

Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system, wherein a size of data transfer is specified in the DMA request and is based on a minimum data transfer size; and submitting the DMA request to an arbitration module to gain access to a bus for transferring the information and while the arbitration module arbitrates between pending DMA requests, the DMA module monitors status from plural buffer slots and before the DMA request is granted, the DMA module modifies the size of data transfer based on available buffer slots.

US Patent:

8065454, Nov 22, 2011

Filed:

Aug 20, 2009

Appl. No.:

12/544658

Inventors:

Bradley S. Sonksen - Rancho Santa Margarita CA, US
Vi Chau - Laguna Niguel CA, US
Rajendra R. Gandhi - Laguna Niguel CA, US

Assignee:

QLOGIC, Corporation - Aliso Viejo CA

International Classification:

G06F 13/00
G06F 3/00
G06F 12/00

US Classification:

710 72, 710 8, 710 10, 710 62, 710 63, 710 15, 710313, 711 1, 711 6, 711202

Abstract:

An adapter having a plurality of functions and a plurality of ports, in which the mapping between functions and ports is configurable. In certain embodiments, device memory can be programmed with a desired mapping scheme that overrides a default mapping scheme for the adapter. In certain embodiments, device memory can be reprogrammed with a different desired mapping to enable the adapter to dynamically respond to system conditions.

US Patent:

8095978, Jan 10, 2012

Filed:

Jun 11, 2007

Appl. No.:

11/761279

Inventors:

Rajendra R. Gandhi - Laguna Niguel CA, US
Parag P. Mehta - Ladera Ranch CA, US

Assignee:

QLOGIC, Corporation - Aliso Viejo CA

International Classification:

G06F 21/00

US Classification:

726 20

Abstract:

A method and a host bus adapter (HBA) are provided. The HBA includes a first port that is enabled for use in a storage area network; and a second port that is enabled after a user acquires a transceiver with a security key, wherein the HBA firmware reads the security key and validates the transceiver and enables a function for the second port. The method includes coupling a transceiver to an inactive port, wherein the transceiver stores a security key; validating the transceiver by reading the security key; enabling a function for the inactive port; downloading a software component for the inactive port; and operating the host bus adapter with more than one functional port.

US Patent:

8225018, Jul 17, 2012

Filed:

Aug 30, 2011

Appl. No.:

13/221737

Inventors:

Bradley S. Sonksen - Rancho Santa Margarita CA, US
Vi Chau - Laguna Niguel CA, US
Rajendra R. Gandhi - Laguna Niguel CA, US

Assignee:

QLOGIC, Corporation - Aliso Viejo CA

International Classification:

G06F 13/00
G06F 3/00
G06F 12/00

US Classification:

710 72, 710 8, 710 10, 710 15, 710 62, 710 63, 710313, 711 1, 711 6, 711202

Abstract:

An adapter having a plurality of functions and a plurality of ports, in which the mapping between functions and ports is configurable. In certain embodiments, device memory can be programmed with a desired mapping scheme that overrides a default mapping scheme for the adapter. In certain embodiments, device memory can be reprogrammed with a different desired mapping to enable the adapter to dynamically respond to system conditions.

US Patent:

8250252, Aug 21, 2012

Filed:

Jun 29, 2010

Appl. No.:

12/826105

Inventors:

Dharma R. Konda - Aliso Viejo CA, US
Rajendra R. Gandhi - Laguna Niguel CA, US

Assignee:

QLOGIC, Corporation - Aliso Viejo CA

International Classification:

G06F 13/00

US Classification:

710 22, 710260, 718 1, 718100, 711203

Abstract:

A system is provided. The system comprises a plurality of virtual machines executed by a computing system for sending and receiving information; and an adapter presented to the plurality of virtual machines as a shared hardware resource; wherein the adapter includes a direct memory access (DMA) module that is used for transferring control blocks to and from a computing system memory to an adapter memory, where the computing system memory has dedicated memory locations for each virtual machine to place the control blocks and the adapter memory has dedicated memory locations for storing the control blocks generated by each of the plurality of virtual machines; wherein the DMA module stores a context for each virtual machine that includes a computing system memory address assigned to each of the virtual machine and a quality of service entry that is used to limit a number of available control blocks that are transferred for a virtual machine at any given time when a control block from another virtual machine is available and there is storage space available to store the available control block for the other virtual machine.