Rajesh S Parthasarathy from 1209 NE Creeksedge Dr, Beaverton, OR 97124, age 51

Us Patents

Exception Handling For Single Instructions With Multiple Data
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US Patent:

6944745, Sep 13, 2005
Filed:

Aug 26, 2002
Appl. No.:

10/229317
Inventors:

Rajesh S. Parthasarathy - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F009/44
G06F015/80
US Classification:

712 22, 712244
Abstract:

Processing a micro-operation may include providing information to an event handler indicating which of multiple sets of data caused events during processing of a single instruction on multiple sets of data in parallel. The event handler may access the provided information to simplify handling of data sets that did not cause an event. Handling the data sets may include the event handler determining a result for data sets that caused events, accessing results determined outside of the event handler for data sets that did not cause an event, and accumulating all of the results.

Performing Repeat String Operations
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US Patent:

7100029, Aug 29, 2006
Filed:

Aug 28, 2002
Appl. No.:

10/233155
Inventors:

Xiang Zou - Beaverton OR, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Madhavan Parthasarathy - Beaverton OR, US
Dion Rodgers - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/38
G06F 9/00
US Classification:

712300, 712220
Abstract:

Performing repeat string operations can include aligning a source data location or a destination data location to a location divisible by a predetermined integer, the aligning including performing a string operation using data having a size equal to the operand size. After aligning, a string operation can be performed using data having a size larger than the operand size. Performing repeat string operations can include issuing a first predetermined number of iterations if an operand size is a predetermined size, and issuing a second predetermined number of iterations otherwise. Performing repeat string operations can include determining that a requested number of iterations in a repeat string operation is within a predetermined multi-number range and issuing exactly the requested number of iterations for any value of the requested number within that range.

Apparatus And Method For Maintaining A Floating Point Data Segment Selector
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US Patent:

7185181, Feb 27, 2007
Filed:

Aug 5, 2002
Appl. No.:

10/212911
Inventors:

Rajesh S. Parthasarathy - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/38
G06F 9/445
US Classification:

712218
Abstract:

An apparatus and method for maintaining a floating point data segment selector are described. In one embodiment, the method includes the detection of a micro-operation of a memory referencing macro-instruction from one or more micro-operations to be retired during a system clock cycle. When the detected micro-operation triggers an event, a micro-code event handler is triggered to initiate an update of a floating point data segment selector information associated with the detected micro-operation. Otherwise, FDS update device is triggered to update the floating point data segment selector information associated with the detected micro-operation.

Support For Nested Fault In A Virtual Machine Environment
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US Patent:

7305592, Dec 4, 2007
Filed:

Jun 30, 2004
Appl. No.:

10/882813
Inventors:

Gilbert Neiger - Portland OR, US
Andrew V. Anderson - Hillsboro OR, US
Steven M. Bennett - Hillsboro OR, US
Jason Brandt - Austin TX, US
Erik Cota-Robles - Portland OR, US
Stalinselvaraj Jeyasingh - Beaverton OR, US
Alain Kägi - Portland OR, US
Sanjoy K. Mondal - San Marcos TX, US
Rajesh Parthasarathy - Hillsboro OR, US
Dion Rodgers - Hillsboro OR, US
Lawrence O. Smith - Beaverton OR, US
Richard A. Uhlig - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 11/00
US Classification:

714 48, 714 42
Abstract:

In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transition of control to a virtual machine monitor (VMM). If this determination is positive, information pertaining to the second fault is stored in a second field, and control is transitioned to the VMM.

Method And Apparatus For A Guest To Access A Memory Mapped Device
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US Patent:

7506121, Mar 17, 2009
Filed:

Dec 30, 2005
Appl. No.:

11/322757
Inventors:

Gilbert Neiger - Portland OR, US
Andrew V. Anderson - Hillsboro OR, US
Steven M. Bennett - Hillsboro OR, US
Rajesh Sankaran Madukkarumukumana - Portland OR, US
Richard A. Uhlig - Hillsboro OR, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Sebastian Schoenberg - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/00
US Classification:

711163
Abstract:

Embodiments of apparatuses, methods, and systems for guests to access memory mapped devices are disclosed. In one embodiment, an apparatus includes evaluation logic and exit logic. The evaluation logic is to determine, in response to an attempt of a guest to access a device using a memory address mapped to the device and based on an access type, whether the access is allowed. The exit logic is to transfer control to a host if the evaluation logic determines that the access is not allowed.

Methods For Supporting Extended Precision Integer Divide Macroinstructions In A Processor
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US Patent:

7523152, Apr 21, 2009
Filed:

Dec 26, 2002
Appl. No.:

10/330896
Inventors:

Patrice L. Roussel - Portland OR, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 7/52
G06F 7/44
US Classification:

708650, 708504
Abstract:

A method for an extended precision integer divide algorithm includes separating an L-bit integer dividend into two equal width integer format portions, a first portion including lower M bits of the integer dividend and a second portion including upper M bits of the integer dividend, where M is equal to L. An N-bit wide integer divisor is converted from an integer format into a floating point format divisor. The first integer portion is converted into a floating point format and divided by the floating point format divisor to obtain a first floating point quotient, which is converted into a first integer format quotient. The second integer portion is converted into a floating point format and divided by the floating point format divisor to obtain a second floating point quotient which is also converted to a second integer format quotient. Then first and second integer format quotients are summed together to generate a third integer format quotient.

Creation Of Logical Apic Id With Cluster Id And Intra-Cluster Id
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US Patent:

7627706, Dec 1, 2009
Filed:

Sep 6, 2007
Appl. No.:

11/850782
Inventors:

Shivnandan D. Kaushik - Portland OR, US
Keshavan K. Tiruvallur - Tigard OR, US
James B. Crossland - Banks OR, US
Sridhar Muthrasanallur - Puyallup WA, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Luke P. Hood - Portland OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 13/24
G06F 13/32
US Classification:

710268
Abstract:

In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

Processor Selection For An Interrupt Identifying A Processor Cluster
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US Patent:

7769938, Aug 3, 2010
Filed:

Sep 6, 2007
Appl. No.:

11/850790
Inventors:

Shivnandan D. Kaushik - Portland OR, US
Keshavan K. Tiruvallur - Tigard OR, US
James B. Crossland - Banks OR, US
Sridhar Muthrasanallur - Puyallup WA, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Luke P. Hood - Portland OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 13/24
G06F 13/32
US Classification:

710268
Abstract:

In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.