Rajiv Gupta

US Patent:

6381676, Apr 30, 2002

Filed:

Dec 7, 2000

Appl. No.:

09/732491

Inventors:

Robert Aglietti - San Jose CA
Rajiv Gupta - Los Altos CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711133, 711129, 711127, 711126

Abstract:

A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.

US Patent:

6408373, Jun 18, 2002

Filed:

May 7, 2001

Appl. No.:

09/850878

Inventors:

Stephen G. Burger - Santa Clara CA
James O. Hays - San Jose CA
Jonathan K. Ross - Sunnyvale CA
William R. Bryg - Saratoga CA
Rajiv Gupta - Los Altos CA
Gary N. Hammond - Campbell CA
Koichi Yamada - San Jose CA

Assignee:

Institute for the Development of Emerging Architectures, LLC - Cupertino CA

International Classification:

G06F 1200

US Classification:

711207, 711209

Abstract:

A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry.

US Patent:

6453389, Sep 17, 2002

Filed:

Jun 25, 1999

Appl. No.:

09/340279

Inventors:

Marcelo Weinberger - San Jose CA
Tomas G. Rokicki - Palo Alto CA
Gadiel Seroussi - Cupertino CA
Rajiv Gupta - Los Altos CA
Neri Merhav - Haifa, IL
Joesp M. Ferrandiz - Palo Alto CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711137, 711213

Abstract:

The method of prefetching data into cache to minimize CPU stall time uses a rough predictor to make rough predictions about what cache lines will be needed next by the CPU. The address difference generator uses the rough prediction and the actual cache miss address to determine the address difference. The prefetch engine builds a data structure to represent address differences and weights them according to the accumulated stall time produced by the cache misses given that the corresponding address is not prefetched. This stall time is modeled as a loss function of the form: The weights in the data structure change as the prefetch engine learns more information. The prefetch engines goal is to predict the cache line needed and prefetch before the CPU requests it.

US Patent:

6470339, Oct 22, 2002

Filed:

Mar 31, 1999

Appl. No.:

09/281876

Inventors:

Alan H. Karp - Palo Alto CA
Rajiv Gupta - Los Altos CA
Arindam Banerji - Sunnyvale CA
Chia-Chiang Chao - Saratoga CA
Ernest Mak - Fremont CA
Sandeep Kumar - San Jose CA
Venkatesh Krishnan - Sunnyvale CA
Guillermo Rozas - Mountain View CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1700

US Classification:

707 8, 707 9, 713182, 713155

Abstract:

A software system that provides access control to resources and that disassociates access rights to resources from references to resources to prevent the formation of large and unwieldy access control lists and to enable advanced decentralized security controls. The software system includes a repository that holds a resource descriptor for each resource including lock/permission pairs. Access to particular resources or groups of resources is provided by providing users with the appropriate keys. The keys are themselves are resources with resource descriptors in the repository. Access rights for users may be revoked by deleting keys from the repository. The software system also provides visibility fields for compartmentalizing access to resources. In addition, the software system provides authorizers that maintain audit trails when critical resource such as keys are passed among users and that enable advanced security control when passing resources among users.

US Patent:

6493712, Dec 10, 2002

Filed:

Aug 17, 1999

Appl. No.:

09/376149

Inventors:

Alan H. Karp - Palo Alto CA
Rajiv Gupta - Los Altos CA
Arindam Banerji - Sunnyvale CA
Chia-Chiang Chao - Saratoga CA
Ernest Mak - Fremont CA
Sandeep Kumar - Santa Clara CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1730

US Classification:

707 6, 707102, 709217, 358 111, 358 113, 358 118

Abstract:

A software system with self-describing attribute vocabularies that enhance the capability of service providers to advertise their resources and that facilitate the addition of new types of attributes and resources to the system. Each self-describing attribute vocabulary is characterized by a corresponding set of attribute properties and a corresponding set of:matching rules that are adapted to the corresponding attribute properties. The software system includes a matching engine that enables a service provider of a resource to describe the resource to the software system in terms of any one or more of the self-describing attribute vocabularies.

US Patent:

6578065, Jun 10, 2003

Filed:

Sep 23, 1999

Appl. No.:

09/405441

Inventors:

Robert Aglietti - San Jose CA
Tomas G. Rokicki - Palo Alto CA
Rajiv Gupta - Los Altos CA

Assignee:

Hewlett-Packard Development Company L.P. - Houston TX

International Classification:

G06F 900

US Classification:

709104, 711 3, 711133, 711141, 707141, 707142, 707143, 707144, 707145, 707146, 709102, 709105, 709106

Abstract:

A system and method for controlling the scheduling of threads in a multi-thread processor system. The multi-thread processor system has a multi-thread processor, a main memory, a cache memory, and a thread scheduler. Information is sent from the cache memory to the thread scheduler for determining which thread the processor is going to execute. The thread scheduler calculates or maintains a figure of merit for each thread executing on the processor. The figure of merit determines which thread to switch to when the current or previous thread has a long latency. The figure of merit define the execution environment as measured by the performance of the cache memory. The figure of merit can be the owner of a particular thread, the number of data lines accessed by a particular thread which resides in the cache, the number of times a particular thread has hit in the cache over a specified time interval, the thread that installed the data or the thread that was used most recently.

US Patent:

6611910, Aug 26, 2003

Filed:

Oct 12, 1998

Appl. No.:

09/169868

Inventors:

Harshvardhan Sharangpani - Santa Clara CA
Tse-Yu Yeh - Milpitas CA
Michael Paul Corwin - Palo Alto CA
Millind Mittal - Palo Alto CA
Kent G. Fielden - Sunnyvale CA
Dale Morris - Steamboat Springs CO
Rajiv Gupta - Los Altos CA
Michael Schlansker - Los Altos CA
Mircea Poplingher - Palo Alto CA

Assignee:

Idea Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712237, 709238

Abstract:

A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

US Patent:

6629232, Sep 30, 2003

Filed:

Jul 3, 2000

Appl. No.:

09/609911

Inventors:

Ken Arora - Los Gatos CA
Harshvardhan Sharangpani - Santa Clara CA
Rajiv Gupta - Los Altos CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

712 29, 712 23

Abstract:

Interconnect-dominated large register files are reduced in chip area and delay time. A register file in a processor having a number of execution units is divided into multiple copies. Different groups of execution units can read from and write to their own copy of the file registers by a set of local read and write ports. All of the register-file copies are synchronized by writing data from the execution units to remote write ports in at least some registers in other copies of the register file. Each copy can be divided into local and global registers. While all copies of the global registers continue to be written by the remote write ports, the local registers can be written only by a local cluster of execution units. Alternatively or additionally, all of the execution units can write to their local register-file copy, but only some of the units can write the global registers in all copies of the register file.