Rajiv Gupta

US Patent:

58023747, Sep 1, 1998

Filed:

Apr 15, 1997

Appl. No.:

8/839731

Inventors:

Rajiv Gupta - Ossining NY
Michael Abraham Epstein - Spring Valley NY

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

G06F 944

US Classification:

395706

Abstract:

A barrier is used to synchronize parallel processors. The barrier is "fuzzy", i. e. it includes several instructions in each instruction stream. None of the processors performing related tasks can execute an instruction after its respective fuzzy barrier until the others have finished the instruction immediately preceding their respective fuzzy barriers. Processors therefore spend less time waiting for each other. A state machine is used to keep track of synchronization states during the synchronization process.

US Patent:

53177347, May 31, 1994

Filed:

Aug 29, 1989

Appl. No.:

7/400178

Inventors:

Rajiv Gupta - Ossining NY

Assignee:

North American Philips Corporation - New York NY

International Classification:

G06F 1300

US Classification:

395650

Abstract:

A method of synchronizing the parallel processors of a multiple instruction stream multiprocessor employs a limited number of register channels, which may be re-used, for enforcing cross-stream data or event dependencies by passing data or event notifications in a synchronizing fashion. Cross-stream dependencies which by virtue of identified "synchronization redundancey" do not require enforcement by register channels are passed by writing to and reading from ordinary shared memory. A compiling method schedules the instructions into parallel instruction streams by reference to a directed acyclic graph (DAG), in a manner to minimize the production of cross-stream dependencies. The scheduling is determined beginning from the highest nodes in the DAG and proceeding to nodes in order of descending node height in a manner tending and tends to assign whole sub-graphs of the DAG to different processors.

US Patent:

53033779, Apr 12, 1994

Filed:

Mar 27, 1990

Appl. No.:

7/500627

Inventors:

Rajiv Gupta - Ossining NY
Chi-Hung Chi - Croton-on-Hudson NY

Assignee:

North American Philips Corporation - New York NY

International Classification:

G06F 944

US Classification:

395700

Abstract:

Method for compiling program instructions to reduce instruction cache misses and instruction cache pollution. The program is analyzed for instructions which result in a non-sequential transfer of control in the program. The presence of branch instructions and program loops are identified and analyzed. The instructions are placed in lines, and the lines are placed in a sequence to minimize potential misses.

US Patent:

57872724, Jul 28, 1998

Filed:

Jun 10, 1997

Appl. No.:

8/871562

Inventors:

Rajiv Gupta - Ossining NY
Michael Abraham Epstein - Spring Valley NY

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

G06F 1516

US Classification:

395553

Abstract:

A barrier is used to synchronize parallel processors. The barrier is "fuzzy", i. e. it includes several instructions in each instruction stream. None of the processors performing related tasks can execute an instruction after its respective fuzzy barrier until the others have finished the instruction immediately preceding their respective fuzzy barriers. Processors therefore spend less time waiting for each other. A state machine is used to keep track of synchronization states during the synchronization process.

US Patent:

51270927, Jun 30, 1992

Filed:

Jun 15, 1989

Appl. No.:

7/366570

Inventors:

Rajiv Gupta - Ossining NY
Michael A. Epstein - Spring Valley NY

Assignee:

North American Philips Corp. - New York NY

International Classification:

G06F 1516

US Classification:

395375

Abstract:

A Multiple Instruction Stream Multiple Data Stream (MIMD) parallel processing apparatus and compiling method for effectuating collective branching of execution by the processors includes specialized branch and fuzzy barrier units which operate with respect to special instructions scheduled in unshaded regions of the instruction streams of the processors involved in a collective branch. A special compare instruction is scheduled in a first unshaded region of only one of the processors while a special jump instruction is scheduled in the next unshaded region of the instruction stream of the other involved processors. By the special jump instruction, the other processors use the special compare result which is simultaneously passed to each of them by the branch unit for determining the execution branch. The barrier unit provides fuzzy barrier synchronization assuring that the correct compare result is used in this determination.