Rajiv J Joshi

US Patent:

7898894, Mar 1, 2011

Filed:

Apr 12, 2006

Appl. No.:

11/402401

Inventors:

Leland Chang - New York NY, US
Rajiv V. Joshi - Yorktown Heights NY, US
Stephen V. Kosonocky - Wilton CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/41
G11C 8/16
G11C 5/06

US Classification:

36523005, 365154, 365 63, 365 72

Abstract:

The present invention provides an improved SRAM cell. Specifically, the present invention provides an SRAM cell having one or more sets of stacked transistors for isolating the cell during a read operation. Depending on the embodiment, the SRAM cell of the present invention can have eight or ten transistors. Regardless, the SRAM cell of the present invention typically includes separate/decoupled write word and read word lines, a pair of cross-coupled inverters, and a complimentary pair of pass transistors that are coupled to the write word line. Each set of stacked transistors implemented within the SRAM cell has a transistor that is coupled to a bit line as well as the read word line.

US Patent:

55258280, Jun 11, 1996

Filed:

Aug 23, 1994

Appl. No.:

8/294897

Inventors:

Ernest Bassous - Bronx NY
Jean-Marc Halbout - Larchmont NY
Subramanian S. Iyer - Yorktown Heights NY
Rajiv V. Joshi - Yorktown Heights NY
Vijay P. Kesan - Ridgefield CT
Michael R. Scheuermann - Katonah NY
Massimo A. Ghioni - Peekskill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 3107
H01L 31108

US Classification:

257457

Abstract:

Silicon-VLSI-compatible photodetectors, in the form of a metal-semiconductor-metal photodetector (MSM-PD) or a lateral p-i-n photodetector (LPIN-PD), are disclosed embodying interdigitated metallic electrodes on a silicon surface. The electrodes of the MSM-PD have a moderate to high electron and hole barrier height to silicon, for forming the Schottky barriers, and are fabricated so as to be recessed in the surface semiconducting layer of silicon through the use of self-aligned metallization either by selective deposition or by selective reaction and etching, in a manner similar to the SALICIDE concept. Fabrication is begun by coating the exposed Si surface of a substrate with a transparent oxide film, such that the Si/oxide interface exhibits low surface recombination velocity. The interdigitated pattern is then etched through the oxide film by lithography to expose the Si surface and metallic electrode members are formed selectively in the exposed Si surface, using self-aligned metallization to produce thin interdigitated electrodes recessed below the silicon surface, which itself may be on a comparatively thin Si layer. The electrodes may be spaced to minimize the interdigital carrier transit time and maximize the sensitivity and the entire process and structure are compatible with conventional silicon integrated circuit (IC) technology.

US Patent:

60348879, Mar 7, 2000

Filed:

Aug 5, 1998

Appl. No.:

9/129827

Inventors:

Arunava Gupta - Valley Cottage NY
Rajiv V. Joshi - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1300

US Classification:

365171

Abstract:

A magnetic tunneling junction cell for use in memory and logic switching applications is formed with a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer interposed between said first and second ferromagnetic layers to form a magnetic tunnel junction element. The cell further includes a write conductor which has a first conductor segment aligned in a first direction and located proximate to the first ferromagnetic layer and a second conductor segment aligned in a second direction, substantially orthogonal to the first direction and located proximate to the second ferromagnetic layer. The write conductor is terminated by a capacitive structure which allows a bidirectional current to be established in the write conductor using a monopolar write voltage and only a single port write terminal. The bidirectional current writes a high impedance state into the cell in a first current direction and a low impedance state into the cell in a second current direction. Preferably, the first and second ferromagnetic layers are formed with a half-metallic ferromagnetic material which features near total spin polarization, resulting in a cell having near ideal switching characteristics.

US Patent:

49740563, Nov 27, 1990

Filed:

May 22, 1987

Appl. No.:

7/052825

Inventors:

Stephen B. Brodsky - Valley Cottage NY
Dan Moy - Bethel CT
Rajiv V. Joshi - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2962
H01L 2978

US Classification:

357 71

Abstract:

A gate structure for integrated circuit devices which includes a work function layer, a low resistivity layer, and an electrically conductive barrier layer between the two other layers to prevent the other two layers from intermixing. The work function controlling layer is preferably selected from the group of tungsten, molybdenum, their silicides, or a combination thereof.

US Patent:

20200168290, May 28, 2020

Filed:

Jan 28, 2020

Appl. No.:

16/774505

Inventors:

- Armonk NY, US
Swagath Venkataramani - Yonkers NY, US
Rajiv Joshi - Yorktown Heights NY, US
Karthik V. Swaminathan - Mount Kisco NY, US
Schuyler Eldridge - Ossining NY, US
Pradip Bose - Yorktown Heights NY, US

International Classification:

G11C 29/50
G06N 3/063
G06N 3/04
G06N 3/08

Abstract:

A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.

US Patent:

20190205793, Jul 4, 2019

Filed:

Dec 28, 2017

Appl. No.:

15/857103

Inventors:

- Armonk NY, US
Avijit CHATTERJEE - White Plains NY, US
Rajiv JOSHI - Yorktown Heights NY, US
John J. THOMAS - Fishkill NY, US

International Classification:

G06N 99/00
G06F 17/30
G06F 7/08

Abstract:

Method and apparatus for generating profiles using machine learning and influencing online interactions are provided. The methods include generating a user profile specifying a plurality of attribute values for a plurality of principle attributes, by processing a corpus of electronic documents using a first trained machine learning model. In an embodiment, the method further comprises generating a provider profile specifying a plurality of attribute values for the plurality of principle attributes, for each of a plurality of providers, by processing a respective corpus of electronic documents associated with each respective provider using a second trained machine learning model. A plurality of match coefficients based on comparing the user profile and the plurality of provider profiles are determined. Finally, one or more online interactions between the user and the target provider are influenced based on the determined match coefficients.

US Patent:

20190205950, Jul 4, 2019

Filed:

Dec 28, 2017

Appl. No.:

15/856883

Inventors:

- Armonk NY, US
Avijit CHATTERJEE - White Plains NY, US
Rajiv JOSHI - Yorktown Heights NY, US
John J. THOMAS - Fishkill NY, US

International Classification:

G06Q 30/02
H04L 29/08
G06Q 30/06
G06F 17/30
G06F 15/18

Abstract:

Method and apparatus for generating profiles using machine learning and influencing online interactions are provided. The methods include receiving, from a first user of a plurality of users, a first set of electronic documents, where each electronic document in the first set of electronic documents corresponds to a respective user in the plurality of users. The methods also include identifying a plurality of user profiles, where each of the plurality of user profiles was generated by processing a corpus of electronic documents associated with each respective user using a first trained machine learning model. The methods include determining a plurality of match coefficients, based on comparing a plurality of user profiles associated with each respective user in the plurality of users, filtering the first set of electronic documents based on the plurality of match coefficients, and providing the filtered first set of electronic documents to the first user.

US Patent:

20180358110, Dec 13, 2018

Filed:

Jun 13, 2017

Appl. No.:

15/621281

Inventors:

- Armonk NY, US
Swagath Venkataramani - Yonkers NY, US
Rajiv Joshi - Yorktown Heights NY, US
Karthik V. Swaminathan - Mount Kisco NY, US
Schuyler Eldridge - Ossining NY, US
Pradip Bose - Yorktown Heights NY, US

International Classification:

G11C 29/50
G06N 3/063
G06N 3/04
G06N 3/08

Abstract:

A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.