Raj N Sundararaman

US Patent:

20070001737, Jan 4, 2007

Filed:

Sep 29, 2005

Appl. No.:

11/238779

Inventors:

Raj Sundararaman - Mission Viejo CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

G06F 1/04

US Classification:

327291000

Abstract:

A system and method are provided for producing two asymmetric duty cycle clock phases as outputs, where the duration of the active phase may be varied to generate clock signal having an asymmetric duty cycle. A circuit configured according to the invention includes a monostable clock generator configured to produce an asymmetric duty cycle clock phase from a reference clock input, a delayed phase generator configured to produce two clock phases whose falling edges are delayed with respect to the input signals, and a second phase generator configured to produce a second asymmetric duty cycle clock phase. The phase may be programmable by including a variable resistor network that can be varied in response to control signals.

US Patent:

20070001751, Jan 4, 2007

Filed:

Sep 29, 2005

Appl. No.:

11/238768

Inventors:

Raj Sundararaman - Mission Viejo CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

G05F 1/10

US Classification:

327541000

Abstract:

A system and related method are provided for producing a reference bias current that varies within a limited threshold from its nominal value based on band gap voltage, and that generates the bias current substantially independent from process and temperature. In one embodiment, the invention provides a process dependant voltage generator, a temperature independent voltage generator, and a voltage to current converter receiving inputs from bandgap voltage generator and a temperature independent voltage generator to generate a bias current that is substantially independent from process and temperature.

US Patent:

20070001101, Jan 4, 2007

Filed:

Sep 28, 2005

Appl. No.:

11/238425

Inventors:

Raj Sundararaman - Mission Viejo CA, US
Chi-Shao Lin - Mission Viejo CA, US
Jiafu Luo - Irvine CA, US
Richard Mann - Torrance CA, US
Zeynep Toros - Aliso Viejo CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H01J 40/14

US Classification:

25021400R

Abstract:

An electronic device is provided such as a programmable rise/fall time control circuit, for example, that delivers a continuous and near linear rising/falling slope of a control signal, with programmability that can be implemented in future CMOS image sensor devices. This device includes a programmability block for reset or transfer gate signals. The programmability block includes two inputs: an input bias current and a signal from the control bits. The programmability block further includes two similar internal circuit blocks, one for generating a fall time control signal, and one for generating a rise time control signal. Additionally the programmability block includes two outputs; a fall time control signal, and a rise time control signal. The device further includes a reset or transfer gate buffer configured as an inverter. The reset or transfer gate buffer includes three input signals: The fall time control signal and rise time control signal from the programmability block, and an INT Reset signal. Furthermore, the reset or transfer gate buffer includes an output reset or transfer gate signal. The device is configured to take an input bias current, and by controlling the transconductance of internal circuitry provide a tapered rise and fall time signal to a reset or transfer gate of a CMOS image sensor that is programmable.