Ralph E Bellofatto from 187 Topsfield Rd, Wenham, MA 01984, age 67, Phone: 2034318306

Us Patents

Power Throttling Of Collections Of Computing Elements
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US Patent:

8001401, Aug 16, 2011
Filed:

Jun 26, 2007
Appl. No.:

11/768752
Inventors:

Ralph E. Bellofatto - Ridgefield CT, US
Paul W. Coteus - Yorktown Heights NY, US
Paul G. Crumley - Yorktown Heights NY, US
Alan G. Gara - Mount Kidsco NY, US
Mark E. Giampapa - Irvington NY, US
Thomas M. Gooding - Rochester MN, US
Rudolf A. Haring - Cortlandt Manor NY, US
Mark G. Megerian - Rochester MN, US
Martin Ohmacht - Yorktown Heights NY, US
Don D. Reed - Mantorville MN, US
Richard A. Swetz - Mahopac NY, US
Todd Takken - Brewster NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1/26
US Classification:

713320, 713300, 713310, 713321, 713322, 713323, 713324, 713330, 713340
Abstract:

An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.

Method And Apparatus To Debug An Integrated Circuit Chip Via Synchronous Clock Stop And Scan
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US Patent:

8140925, Mar 20, 2012
Filed:

Jun 26, 2007
Appl. No.:

11/768791
Inventors:

Ralph E. Bellofatto - Ridgefield CT, US
Matthew R. Ellavsky - Rochester MN, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Thomas M. Gooding - Rochester MN, US
Rudolf A. Haring - Cortlandt Manor NY, US
Lance G. Hehenberger - Leander TX, US
Martin Ohmacht - Yorktown Heights NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G01R 31/28
G06F 1/12
US Classification:

714731, 713400
Abstract:

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Reproducibility In A Multiprocessor System
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US Patent:

8595554, Nov 26, 2013
Filed:

May 5, 2010
Appl. No.:

12/774475
Inventors:

Ralph A. Bellofatto - Ridgefield CT, US
Dong Chen - Croton On Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Noel A. Eisley - Yorktown Heights NY, US
Alan Gara - Mount Kisco NY, US
Thomas M. Gooding - Rochester MN, US
Rudolf A. Haring - Cortlandt Manor NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Gerard V. Kopcsay - Yorktown Heigths NY, US
Thomas A. Liebsch - Arlington SD, US
Martin Ohmacht - Yorktown Heights NY, US
Don D. Reed - Rochester MN, US
Robert M. Senger - Tarrytown NY, US
Burkhard Steinmacher-Burow - Esslingen, DE
Yutaka Sugawara - White Plains NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 11/00
US Classification:

714 27, 714 30, 714731
Abstract:

Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.

Method And Infrastructure For Cycle-Reproducible Simulation On Large Scale Digital Circuits On A Coordinated Set Of Field-Programmable Gate Arrays (Fpgas)
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US Patent:

8640070, Jan 28, 2014
Filed:

Nov 8, 2010
Appl. No.:

12/941834
Inventors:

Sameh W Asaad - Briarcliff Manor NY, US
Ralph E Bellofatto - Ridgefield CT, US
Bernard Brezzo - Somers NY, US
Charles L Haymes - Fair Lawn NJ, US
Mohit Kapur - Sleepy Hollow NY, US
Benjamin D Parker - Peekskill NY, US
Thomas Roewer - Danbury CT, US
Jose A Tierno - Stamford CT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
US Classification:

716116, 716106, 716117
Abstract:

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom.

System And Method For Creating And Editing Documents
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US Patent:

20030097640, May 22, 2003
Filed:

Jul 25, 2002
Appl. No.:

10/201914
Inventors:

Steven Abrams - New City NY, US
Ralph Bellofatto - Ridgefield CT, US
Robert Fuhrer - New York NY, US
Daniel Oppenheim - Croton on Hudson NY, US
James Wright - Chappaqua NY, US
Richard Boulanger - Somerset MA, US
Neil Leonard - Jamaica Plain MA, US
David Mash - Framingham MA, US
Michael Rendish - North Sandwich NH, US
Joseph Smith - Framingham MA, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F015/00
US Classification:

715/530000, 715/501100
Abstract:

A system for creating and editing documents may include a reference view function which allows a user to quickly and easily refer to data that may not be included in a document. The inventive system may also include a function for saving and restoring view configurations to ensure that valuable ideas may be stored and recalled, and/or a function for tracking of motivic re-use of data.

Configurable Memory System And Method For Providing Atomic Counting Operations In A Memory Device
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US Patent:

20090006800, Jan 1, 2009
Filed:

Jun 26, 2007
Appl. No.:

11/768812
Inventors:

Ralph E. Bellofatto - Ridgefield CT, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Martin Ohmacht - Yorktown Heights NY, US
Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

G06F 12/00
US Classification:

711170, 711E12084
Abstract:

A memory system and method for providing atomic memory-based counter operations to operating systems and applications that make most efficient use of counter-backing memory and virtual and physical address space, while simplifying operating system memory management, and enabling the counter-backing memory to be used for purposes other than counter-backing storage when desired. The encoding and address decoding enabled by the invention provides all this functionality through a combination of software and hardware.

Multi-Petascale Highly Efficient Parallel Supercomputer
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US Patent:

20110219208, Sep 8, 2011
Filed:

Jan 10, 2011
Appl. No.:

13/004007
Inventors:

Sameh Asaad - Yorktown Heights NY, US
Ralph E. Bellofatto - Yorktown Heights NY, US
Michael A. Blocksome - Rochester MN, US
Matthias A. Blumrich - Yorktown Heights NY, US
Peter Boyle - Yorktown Heights NY, US
Jose R. Brunheroto - Yorktown Heights NY, US
Dong Chen - Yorktown Heights NY, US
George L. Chiu - Yorktown Heights NY, US
Norman Christ - Yorktown Heights NY, US
Paul W. Coteus - Yorktown Heights NY, US
Kristan D. Davis - Rochester MN, US
Gabor J. Dozsa - Yorktown Heights NY, US
Alexandre E. Eichenberger - Yorktown Heights NY, US
Noel A. Eisley - Yorktown Heights NY, US
Matthew R. Ellavsky - Rochester MN, US
Kahn C. Evans - Rochester MN, US
Bruce M. Fleischer - Yorktown Heights NY, US
Thomas W. Fox - Yorktown Heights NY, US
Alan Gara - Yorktown Heights NY, US
Mark E. Giampapa - Yorktown Heights NY, US
Thomas M. Gooding - Rochester MN, US
Michael K. Gschwind - Yorktown Heights NY, US
John A. Gunnels - Yorktown Heights NY, US
Shawn A. Hall - Yorktown Heights NY, US
Rudolf A. Haring - Yorktown Heights NY, US
Philip Heidelberger - Yorktown Heights NY, US
Todd A. Inglett - Rochester MN, US
Brant L. Knudson - Rochester MN, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Sameer Kumar - Yorktown Heights NY, US
Amith R. Mamidala - Yorktown Heights NY, US
James A. Marcella - Rochester MN, US
Mark G. Megerian - Rochester MN, US
Douglas R. Miller - Rochester MN, US
Samuel J. Miller - Rochester MN, US
Adam J. Muff - Rochester MN, US
Michael B. Mundy - Rochester MN, US
John K. O'Brien - Yorktown Heights NY, US
Kathryn M. O'Brien - Yorktown Heights NY, US
Martin Ohmacht - Yorktown Heights NY, US
Jeffrey J. Parker - Rochester MN, US
Ruth J. Poole - Rochester MN, US
Joseph D. Ratterman - Rochester MN, US
Valentina Salapura - Yorktown Heights NY, US
David L. Satterfield - Tewksbury MA, US
Robert M. Senger - Yorktown Heights NY, US
Brian Smith - Rochester MN, US
Burkhard Steinmacher-Burow - Boeblingen, DE
William M. Stockdell - Rochester MN, US
Craig B. Stunkel - Yorktown Heights NY, US
Krishnan Sugavanam - Yorktown Heights NY, US
Yutaka Sugawara - Yorktown Heights NY, US
Todd E. Takken - Yorktown Heights NY, US
Barry M. Trager - Yorktown Heights NY, US
James L. Van Oosten - Rochester MN, US
Charles D. Wait - Rochester MN, US
Robert E. Walkup - Yorktown Heights NY, US
Alfred T. Watson - Rochester MN, US
Robert W. Wisniewski - Yorktown Heights NY, US
Peng Wu - Yorktown Heights NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 15/76
G06F 9/06
US Classification:

712 12, 712 29, 712 11, 712E09003
Abstract:

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

Testing And Operating A Multiprocessor Chip With Processor Redundancy
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US Patent:

20130031418, Jan 31, 2013
Filed:

Aug 2, 2011
Appl. No.:

13/196459
Inventors:

Ralph E. Bellofatto - Ridgefield CT, US
Steven M. Douskey - Rochester MN, US
Rudolf A. Haring - Cortlandt Manor NY, US
Moyra K. McManus - Peekskill NY, US
Martin Ohmacht - Yorktown Heights NY, US
Dietmar Schmunkamp - Schoenaich, DE
Krishnan Sugavanam - Elmsford NY, US
Bryan J. Weatherford - Essex Junction VT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 11/28
US Classification:

714 40, 714E11178
Abstract:

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.