Ralph B Iverson

US Patent:

52425070, Sep 7, 1993

Filed:

May 6, 1991

Appl. No.:

7/700333

Inventors:

Ralph B. Iverson - Somerville MA

Assignee:

Boston University - Boston MA

International Classification:

H01L 2900

US Classification:

148 33

Abstract:

A semiconductor fabrication process improves the crystal structure of a polycrystalline semiconductor. Adding impurities in large quantities causes an acceleration of the crystallization without noticeably increasing the number of spontaneous nucleations in the material. The result is a region of relatively larger crystalline grains within the doped region which extend approximately 1. mu. m into the undoped region by the time the entire material has crystallized. Junction devices can be created with better electrical characteristics than ordinary polycrystalline semiconductor devices due to fewer grain boundaries at the electrical junctions. One fabrication technique can result in single crystal devices. Another implementation shows a method for fabricating improved polycrystalline vertical diodes such as solar cells.

US Patent:

48743313, Oct 17, 1989

Filed:

May 9, 1988

Appl. No.:

7/220864

Inventors:

Ralph Iverson - Granada Hills CA

Assignee:

Whittaker Corporation - Los Angeles CA

International Classification:

H01R 1359

US Classification:

439449

Abstract:

The strain relief device is used in combination with a metal electronic cable-connector assembly for high temperature applications and high mechanical shock application. The strain relief shrouds and protects the weld or braze between the cable and connector and also extends over a length of the cable to brace it from bending stress ad strain. The strain relief is generally hollow and tubular, an expanded end thereof being slip fitted over and/or welded to or threaded into an end of the connector and caused to extend over the cable-connector weld or braze, with a narrow end of the strain relief forming a lip surrounding the cable distal of the weld or braze to brace it. Thus, the cable and described connector end fit into the central longitudinal passageway in the strain relief and are enclosed by it. The strain relief can be in a form such that its central portion extends through a bulkhead and can be locked thereto. The strain relief lip can also be lined with one or more elastomeric pads or rings to increase resistance to mechanical shock.

US Patent:

20200089830, Mar 19, 2020

Filed:

Sep 12, 2019

Appl. No.:

16/568984

Inventors:

- Mountain View CA, US
Ralph Benhart IVERSON - Arlington MA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50
G06F 16/28

Abstract:

We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, an average EDT (aEDT) is determined based on the EDT. Point-to-point resistance values of the terminal are generated as a function of the aEDT and a capacitance of the terminal.

US Patent:

20180089353, Mar 29, 2018

Filed:

Sep 22, 2017

Appl. No.:

15/713506

Inventors:

- Mountain View CA, US
Ralph Iverson - Arlington MA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50
G06F 17/30

Abstract:

A method to evaluate a resistor structure is described. In one embodiment, the method includes receiving an input file specifying a resistor structure, modifying at least one aspect of the resistor structure, and polishing data representing the modified resistor structure. The method further comprises, in one embodiment, initializing at least one walk, and performing the walk, and providing an output about the resistor structure based on the performed at least one walk.

US Patent:

20170228492, Aug 10, 2017

Filed:

Jan 23, 2017

Appl. No.:

15/413379

Inventors:

- Mountain View CA, US
Ralph Iverson - Arlington MA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50
G03F 7/20

Abstract:

A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.