Ralph E Lane

US Patent:

7081408, Jul 25, 2006

Filed:

Oct 28, 2004

Appl. No.:

10/975572

Inventors:

Ralph L. Lane - Gilbert AZ, US
Charles D. Hill - Gilbert AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/4763
H01L 23/52

US Classification:

438637, 640589, 257774

Abstract:

Embodiments of a method of forming a tapered via using a receding mask are disclosed. In one embodiment, an etch mask formed on a substrate includes a first aperture in a first photoresist layer and a second, larger aperture in an overlying second photoresist layer. Peripheries of the first and second apertures may be tapered as a result of an out-of-focus exposure. An etching process may be performed to create a tapered via in the substrate, and during this etching process, the first, relatively thinner photoresist layer will recede outwardly toward the aperture in the second photoresist layer. Other embodiments are described and claimed.

US Patent:

7427565, Sep 23, 2008

Filed:

Jun 30, 2005

Appl. No.:

11/173245

Inventors:

Tony Dambrauskas - Mesa AZ, US
Ralph Lane - Gilbert AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/44

US Classification:

438687, 438613, 438667, 257E21575

Abstract:

The present invention uses a two step plasma etch process to create a via contact with an integral bump. After the via and bump have been plated, the semiconductor substrate is planarized to remove the excess metal, using the semiconductor substrate as a planar stop. The bulk silicon substrate surrounding the bumps are plasma etched back to expose the bumps for assembly.