Ralph Douglas Moore

US Patent:

40004600, Dec 28, 1976

Filed:

Jul 1, 1974

Appl. No.:

5/484473

Inventors:

Virendra Kirtanlal Kadakia - Huntington Beach CA
Charles Philip Holt - Rancho Palos Verdes CA
Ralph Crittenden Moore - Cypress CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G01R 1512

US Classification:

324 73R

Abstract:

Apparatus is provided for automatic production testing of large digital circuit modules. A test station, under computer control, applies test bit patterns and clock pulses to the module under test, analyzes the resultant outputs, and isolates any fault found to one or several IC's. The test station contains power supplies and air cooling for the module, and a keyboard display and printer for use by the test operator. Test programs are developed off-line and are loaded from magnetic tape into a disk pack where they are available to the computer. The flip-flops on the module to be tested are used as an extension of the test station through the addition on the module of circuitry to allow the flip-flops to be reconfigured from their normal circuit configuration into a shift register connected at one end to one of the module connector pins. Thus, before a test begins, these flip-flops, in a shift register configuration, may be loaded with test data and then configured back into their normal circuit configuration for the actual test. In this manner, test data may be loaded onto a module either in series into the shift register thus produced, or in parallel onto the module connector pins.

US Patent:

20210392117, Dec 16, 2021

Filed:

Jun 11, 2020

Appl. No.:

16/899479

Inventors:

Ralph Crittenden Moore - Costa Mesa CA, US

International Classification:

H04L 29/06
H04L 12/911
H04L 29/08

Abstract:

This invention presents a method to create tunnel portals for exchange of information between client and server partitions by using protected messages. Tunnel portals replace function call APIs in order to achieve full isolation between client and server portals for security. They are capable of performing efficient multiblock data transfers as well as exchanging commands and responses. Client access to tunnel portals is limited at run time and can be priority-based. Servers can have multiple tunnel portals to access multiple subservers.

US Patent:

20200249852, Aug 6, 2020

Filed:

Jan 31, 2019

Appl. No.:

16/264321

Inventors:

Ralph Crittenden Moore - Costa Mesa CA, US

International Classification:

G06F 3/06

Abstract:

Provides an efficient method for aligned heap allocations based upon spare space management, provides an efficient method for MPU region allocations based upon aligned subregion allocations, and provides integrated block pools for small data blocks with heap backup if size or alignment requirements cannot be met from pools or pools are empty. The operation of malloc( ), calloc( ), realloc( ) and free( ) on pool blocks versus heap blocks is transparent to application code. These methods are suitable for limited-memory, real-time systems as well as for general-purpose systems.

US Patent:

20180239550, Aug 23, 2018

Filed:

Feb 23, 2017

Appl. No.:

15/441065

Inventors:

Ralph Crittenden Moore - Costa Mesa CA, US

International Classification:

G06F 3/06
G06F 12/0802

Abstract:

Provides a bin-type heap where bin sizes can be easily customized to the exact requirements of a specific system by means of a bin size array, thus resulting in greater efficiency and better performance. Also provides enhanced debugging support and self-healing. Intended primarily for embedded and similar systems, which require high performance, deterministic operation, efficient memory utilization, high reliability, and which are characterized by limited block size requirements and ample available idle time.

US Patent:

20150226797, Aug 13, 2015

Filed:

Feb 9, 2015

Appl. No.:

14/617814

Inventors:

Ralph Moore - Costa Mesa CA, US

International Classification:

G01R 31/3177

Abstract:

An operating system uses non-bit aligned test masks to encode compound logical tests within the test mask. Generally, a bit within the test mask will indicate whether the test mask is a bit-aligned test mask or a non-bit-aligned test mask. If the system detects that the test mask in a non-bit-aligned test mask, the system will traverse the test mask to extract bit-aligned sub-masks and perform multi-level logical tests with the bit-aligned sub-masks. Such a system is particularly useful when performing a compound AND-OR logical test involving mutually exclusive event group flags.

US Patent:

20150032986, Jan 29, 2015

Filed:

Jul 29, 2014

Appl. No.:

14/446006

Inventors:

Ralph Moore - Costa Mesa CA, US

International Classification:

G06F 3/06

US Classification:

711171

Abstract:

A system for real-time operating system memory block and message management is disclosed. The real-time operating system enables different processes to migrate an allocated memory block from one type of memory block to another type of memory block, and to reliably release the block back to its correct pool of origin. According to one aspect of the inventive subject matter, a memory management engine allocates memory in a basic type to a first process, and upon a migration request from a second process, convert the allocated memory from the basic type to a message type for the second process. Allocating memory in the basic type can be fast but does not ensure proper release of the memory block to its pool of origin. Converting the basic type to the message type enables the operating system to reliably release the block back to its correct pool of origin from any process.