Ramandeep S Sawhney

US Patent:

6788614, Sep 7, 2004

Filed:

Jun 14, 2001

Appl. No.:

09/881472

Inventors:

Ramandeep S. Sawhney - Richardson TX

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 800

US Classification:

365233, 36518903, 36518908, 36523003, 36523006, 365193, 365194, 365195

Abstract:

A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

US Patent:

6865131, Mar 8, 2005

Filed:

May 20, 2003

Appl. No.:

10/441702

Inventors:

Ramandeep S. Sawhney - Richardson TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C007/00

US Classification:

365222, 365190, 365149, 36523003

Abstract:

Systems, devices, structures, and methods are described that reduce energy consumption during a refresh cycle in a memory device. An isolation signal is held in a non-energized state until the it is determined that another action is to be performed on the section of memory associated with the isolation signal. The isolation accordingly cycles from an energized state to a non-energized state and back for each complete refresh cycle in the section of memory.

US Patent:

7042775, May 9, 2006

Filed:

May 26, 2004

Appl. No.:

10/854686

Inventors:

Ramandeep S. Sawhney - Richardson TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00
G11C 7/10
G11C 8/10

US Classification:

365191, 36518903, 36523003, 365233

Abstract:

A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

US Patent:

7327618, Feb 5, 2008

Filed:

Jan 25, 2006

Appl. No.:

11/338937

Inventors:

Ramandeep S. Sawhney - Richardson TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00
G11C 7/10
G11C 8/00

US Classification:

365196, 365191, 365193, 365194, 365195, 36518908, 36523003, 365233

Abstract:

A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

US Patent:

7349270, Mar 25, 2008

Filed:

Oct 17, 2006

Appl. No.:

11/581926

Inventors:

Ramandeep S. Sawhney - Richardson TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00
G11C 7/10
G11C 8/00

US Classification:

365196, 36518908, 365193, 365194, 36523006

Abstract:

A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

US Patent:

7359258, Apr 15, 2008

Filed:

Oct 17, 2006

Appl. No.:

11/581927

Inventors:

Ramandeep S. Sawhney - Richardson TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00
G11C 7/10
G11C 8/00

US Classification:

365194, 36518908, 365193, 365196, 36523006

Abstract:

A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

US Patent:

20020133663, Sep 19, 2002

Filed:

Mar 15, 2001

Appl. No.:

09/808900

Inventors:

Ramandeep Sawhney - Richardson TX, US

Assignee:

Micron Technology, Inc.

International Classification:

G06F012/00

US Classification:

711/001000

Abstract:

Systems, devices, structures, and methods are described that reduce energy consumption during a refresh cycle in a memory device. An isolation signal is held in a non-energized state until the it is determined that another action is to be performed on the section of memory associated with the isolation signal. The isolation accordingly cycles from an energized state to a non-energized state and back for each complete refresh cycle in the section of memory.