Ramesh A. Iyer - San Jose CA, US Henry D. Nguyen - Houston TX, US Patrick J. Smith - Houston TX, US Jay B. Reimer - Houston TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 13/28
US Classification:
710 22, 710 33, 710 48, 710 52, 710260, 709212
Abstract:
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed. An abort signal is generated when a signal group for a packet being processed by the high level data link controller is not available in a timely manner.
Apparatus And Method For Controlling Block Signal Flow In A Multi Digital Signal Processor Configuration From A Shared Peripheral Direct Memory Controller To High Level Data Link Controller
Patrick Smith - Houston TX, US Jay Reimer - Houston TX, US Ramesh Iyer - San Jose CA, US Henry Nguyen - Houston TX, US
International Classification:
G06F003/00
US Classification:
710/048000
Abstract:
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed.
Apparatus And Method For Distribution Of Signals From A High Level Data Link Controller To Multiple Digital Signal Processor Cores
Patrick Smith - Houston TX, US Jay Reimer - Houston TX, US Ramesh Iyer - San Jose CA, US Henry Nguyen - Houston TX, US
International Classification:
G06F003/00
US Classification:
710/048000
Abstract:
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem. In response to a predetermined condition, the signal groups are forwarded to the identified digital signal processor subsystem. The channel block unit, in response to preselected signal groups, can direct the packet to a digital signal processor subsystem that is different from the digital signal processor subsystem identified by the address signal group.
The present subject matter describes a method and a system for providing automated technical support for a product at a remote end from a Technical Assistance Center (TAC) at a technical support end. The TAC includes a cognitive TAC agent can act as substitute for technical personnel at the TAC. The cognitive TAC agent first learns about the product to which the technical support is to be provided and derives a cognitive dependency graph based on learning. Upon learning, the cognitive TAC agent can automatically provide the technical support for the product using the cognitive dependency graph, without manual intervention of the technical personnel.
Name / Title
Company / Classification
Phones & Addresses
Ramesh Subramaniam Iyer
Ramesh Iyer MD Radiology
4800 Sand Pt Way NE, Seattle, WA 98105 2069872133
Medicine Doctors
Dr. Ramesh S Iyer, Seattle WA - MD (Doctor of Medicine)
Dr. Iyer works in Philadelphia, PA and specializes in Pediatric Cardiology and Clinical Cardiac Electrophysiology. Dr. Iyer is affiliated with Abington Memorial Hospital, Childrens Hospital Of Philadelphia and Grand View Hospital.
Technoedge Consulting LLP - Mumbai, India since Apr 2012
Consultant
Visionary Integration Professionals (VIP Consulting) Nov 2009 - Jun 2012
Manager
MyITGroup, India PVT Limited 2003 - 2007
MyITgroup(India) Pvt Ltd
MyITgroup Jun 2001 - Oct 2007
Managing Director
Qwest Cyber Solutions/Softline Feb 1999 - Jun 2001
Consultant
Xilinx
Director - Pro Audio, Video and Broadcast Bu
Xilinx Apr 2015 - Aug 2015
Director - Video Marketing
Xilinx Apr 2014 - Mar 2015
Director - Business Development
Texas Instruments Mar 2013 - Feb 2014
Director Product Marketing and Business Development - Signal Path Solutions
Texas Instruments Sep 2009 - Mar 2013
Business Line Manager, Enterprise Voice Ip Phone and Desktop Video Conferencing
Education:
Kansas State University 1989 - 1991
Master of Science, Masters, Electrical Engineering
Sardar Vallabhbhai National Institute of Technology, Surat 1982 - 1986
Bachelor of Engineering, Bachelors, Electronics, Communications
St.xavier's School, Surat 1968 - 1982
Skills:
Semiconductors Product Management Wireless Soc Embedded Systems Digital Signal Processors Business Development Asic Product Marketing Ic Analog Arm Strategy Embedded Software Product Development Cross Functional Team Leadership Sales Engineering Start Ups Video Conferencing Telecommunications Hd Video Debugging Cloud Computing Firmware Enterprise Software Enterprise Architecture Microcontrollers Product Launch Voip Android Dsp Architecture
Juniper Networks since Mar 2013
Software Developer
L&T Infotech Nov 2006 - Jan 2013
Software Developer
Samsung Electronics - Suwon, Gyeonggi-do, Korea Feb 2007 - Sep 2010
Software Developer
Alcatel Bell - Antwerp Area, Belgium Jul 2002 - Nov 2006
Software Developer
Indian Institute of Technology, Bombay - Mumbai Area, India Jul 2001 - Jun 2002
Research Assistant
Education:
Indian Institute of Technology, Bombay 2001 - 2002
University of Mumbai 1998 - 2001
NES Junior College 1995 - 1997
Skills:
C++ C Embedded Systems Linux Python Embedded Software Wimax Debugging Software Project Management Snmp Unix Tcp/Ip Rtos Device Drivers Android Core Java Xml Embedded Linux Shell Scripting System Architecture Software Development Fcaps Vxworks Linux Kernel Telecommunications Cmip Ethernet Databases Internet Protocol Suite Sdn Wireless Technologies Network Management Software Oam Atm Networks Data Communication Montavista Product Development Sdk Development Automation Perl