Ramon Bertran Monfort

US Patent:

20210240247, Aug 5, 2021

Filed:

Feb 5, 2020

Appl. No.:

16/782386

Inventors:

- Armonk NY, US
Pradeep Bhadravati PARASHURAMA - Bhadravati, IN
Tobias WEBEL - Schwaebisch-Gmuend, DE
Ramon BETRAN MONFORT - New York NY, US
Alper BUYUKTOSUNOGLU - White Plains NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 1/3206
G06F 1/3296
G06F 9/48
G06F 9/30
G06F 1/324

Abstract:

Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.

US Patent:

20200319994, Oct 8, 2020

Filed:

Apr 4, 2019

Appl. No.:

16/375751

Inventors:

- Armonk NY, US
Ramon BERTRAN MONFORT - New York NY, US
Calvin BULLA - Barcelona, ES
Pradip BOSE - Yorktown Heights NY, US
Hubertus FRANKE - Cortlandt Manor NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 11/36

Abstract:

Embodiments for generating representative microbenchmarks in a computing environment are provided. One or more tracing points may be selected in a target application. Executed instructions and used data of the target application may be dynamically traced according to the one or more tracing points according to a tracing plan. Tracing information of the dynamic tracing may be replicated in an actual computing environment and a simulated computing environment.

US Patent:

20200310516, Oct 1, 2020

Filed:

Apr 1, 2019

Appl. No.:

16/371202

Inventors:

- Armonk NY, US
Preetham M. Lobo - Bangalore, IN
Alper Buyuktosunoglu - White Plains NY, US
Ramon Bertran Monfort - New York NY, US
Pradeep Bhadravati Parashurama - Bhadravati, IN
Archit Kapoor - Bareilly, IN

International Classification:

G06F 1/3206
G06F 9/38

Abstract:

Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate.

US Patent:

20200210229, Jul 2, 2020

Filed:

Jan 1, 2019

Appl. No.:

16/237747

Inventors:

- Armonk NY, US
Alper Buyuktosunoglu - White Plains NY, US
Pradip Bose - Yorktown Heights NY, US
Ramon Bertran Monfort - New York NY, US

International Classification:

G06F 9/48
G06F 1/26
G06F 8/41
G06F 9/50

Abstract:

Preferred embodiments of systems and methods are disclosed to reduce a minimal working voltage, Vmin, and/or increase the frequency of Vmin while executing multithreaded computer programs with better reliability, efficiency, and performance. A computer complier complies multiple copies of high-level code, each with different a different set of resource allocators so system resources are allocated during simultaneous execution of multiple threads in a way that allows reducing Vmin at a given reference voltage frequency and/or increasing the frequency of Vmin at a given Vmin value.

US Patent:

20200159586, May 21, 2020

Filed:

Nov 16, 2018

Appl. No.:

16/194252

Inventors:

- Armonk NY, US
Karthik V. Swaminathan - Mount Kisco NY, US
Ramon Bertran Monfort - New York NY, US
Alper Buyuktosunoglu - White Plains NY, US
Pradip Bose - Yorktown Heights NY, US

International Classification:

G06F 9/50

Abstract:

Applications on different processing elements have different characteristics such as latency versus bandwidth sensitivity, memory level parallelism, different memory access patterns and the like. Interference between applications due to contention at different sources leads to different effects on performance and is quantified. A method for contention-aware resource provisioning in heterogeneous processors includes receiving stand-alone performance statistics for each processing element for a given application. Multi-core performance slowdown can be computed from the received stand-alone performance statistics. When a request to provision an application on the heterogeneous processors is received, application performance requirements of the application can be determined and a bandwidth for the application can be provisioned based on the application performance requirements and the computed multi-core performance slowdown parameter.

US Patent:

20200159691, May 21, 2020

Filed:

Nov 16, 2018

Appl. No.:

16/194247

Inventors:

- Armonk NY, US
Ramon Bertran Monfort - New York NY, US
Alper Buyuktosunoglu - White Plains NY, US
Pradip Bose - Yorktown Heights NY, US
Nandhini Chandramoorthy - Yorktown Heights NY, US
Chen-Yong Cher - Port Chester NY, US

International Classification:

G06F 15/78
G06F 1/26

Abstract:

A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (V), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.

US Patent:

20200110656, Apr 9, 2020

Filed:

Dec 6, 2019

Appl. No.:

16/706195

Inventors:

- Armonk NY, US
Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Pierce I-Jen Chuang - Briarcliff Manor NY, US
Preetham M. Lobo - Bangalore, IN
Ramon Bertran Monfort - New York NY, US
Phillip John Restle - Katonah NY, US
Tobias Webel - Schwaebisch Gmuend, DE

International Classification:

G06F 11/07
G06F 1/28
G06F 1/324
G06F 1/30
G06F 9/38

Abstract:

Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

US Patent:

20180267867, Sep 20, 2018

Filed:

Mar 15, 2017

Appl. No.:

15/459788

Inventors:

- Armonk NY, US
Alper Buyuktosunoglu - White Plains NY, US
Jingwen Leng - Yorktown Heights NY, US
Ramon Bertran Monfort - Bronx NY, US

International Classification:

G06F 11/16

Abstract:

A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures. The method additionally includes performing an error recovery operation that replays the set of operations by the original co-processor and the redundant co-processor, responsive to identifying a mismatch between the respective execution signatures.