Randy E Mckee

US Patent:

49786342, Dec 18, 1990

Filed:

Jul 25, 1989

Appl. No.:

7/385327

Inventors:

Masaaki Yashiro - Plano TX
Randy McKee - Plano TX
Gishi Chung - Dallas TX
Kiyoshi Shirai - Dallas TX
Clarence Teng - Plano TX
Donald J. Coleman - Plano TX

Assignee:

Texas Instruments, Incorporated - Dallas TX

International Classification:

H01L 21265

US Classification:

437 52

Abstract:

The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells allows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistors of the memory cells.

US Patent:

50175068, May 21, 1991

Filed:

Jul 25, 1989

Appl. No.:

7/385344

Inventors:

Randy McKee - Plano TX
Gishi Chung - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2170

US Classification:

437 52

Abstract:

The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. A DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells alows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistor of the memory cells.