Randy L Nash

US Patent:

49532103, Aug 28, 1990

Filed:

Feb 22, 1990

Appl. No.:

7/483536

Inventors:

Paul E. McGlynn - Decatur GA
Randy D. Nash - Dacula GA

Assignee:

Hayes Microcomputer Products, Inc. - Norcross GA

International Classification:

H01B 138

US Classification:

380 48

Abstract:

A method for feature negotiations between two synchronous modems. To engage in negotiations a modem must be configured to support synchronous operation, a data transfer rate of at least 4800 bits per second, and at least one non-default feature. After the orginating modem and the answering modem have completed standard handshaking sequences the originating modem initiates the negotiations by sending a list of supported features. The answering modem responds by confirming that all the features are supported, by returning a subset of the features list, or by sending a different features list. If the answering modem did not confirm the list then the originating modem responds to the subset or to the different list by confirming the subset or different list, by returning a subset of the different list, or by sending another different list. If the originating modem does not initiate the negotiations, if the answering modem does not respond to the list sent by the originating modem, or if negotiations are not completed within a predetermined time after completion of the standard handshaking sequences, then the modems use standard (default) features.

US Patent:

49052829, Feb 27, 1990

Filed:

Oct 19, 1988

Appl. No.:

7/259882

Inventors:

Paul E. McGlynn - Decatur GA
Randy D. Nash - Dacula GA

Assignee:

Hayes Microcomputer Products, Inc. - Norgross GA

International Classification:

H01B 138

US Classification:

380 48

Abstract:

A feature negotiation protocol for synchronous operation and a dynamically adjustable retraining sequence. An originating modem, after completing conventional or standard handshaking sequences, sends a list of desired features to an answering modem. The answering modem either concurs with the desired features, if they are all supported, or sends, back to the originating modem, a list of those features which are supported by the answering modem. After the end of a negotiation time-out period, both modems begin operation using the features which are common to both modems or by using default (standard) features for operation. If the adjustable duration retraining sequence is selected then each modem will measure the elapsed time since the end of its last transmission and, at the beginning of its next transmission, send a retraining sequence which is dependent upon this elapsed time. Likewise, each modem will measure the amount of elapsed time since the end of its last reception and expect to receive a retraining sequence which is dependent upon this elapsed time. The adjustable duration retraining sequence generally operates to reduce the total retraining sequence and thereby increases the data throughput rate.

US Patent:

48688649, Sep 19, 1989

Filed:

Apr 1, 1988

Appl. No.:

7/177534

Inventors:

Taruna Tjahjadi - Norcross GA
Cynthia A. Panella - Alpharetta GA
Matthew F. Easley - Decatur GA
Randy D. Nash - Dacula GA
Steven R. Sweitzer - San Carlos CA
John N. Martin - Atlanta GA
German E. Correa - Marietta GA
George R. Thomas - Marietta GA

Assignee:

Hayes Microcomputer Products, Inc. - Norcross GA

International Classification:

H04M 1100

US Classification:

379 98

Abstract:

An improved V. 22 bis 2400 bits per second (bps) handshake sequence detector. An incoming phase keyed (PSK) handshake sequence is autocorrelated using a frequency shift keyed (FSK) receiver (101). The autocorrelated signal is then filtered by a low pass filter (106). The autocorrelated, low pass filtered signal is then alternately fed, at a 1200 Hz rate, to two detectors (114,116). Each of the detectors (114,116) looks for one half of the handshake sequence. The output of each detector (114,116) is provided to an OR-gate (122). The 2400 bps handshake sequence is declared to be detected when either one or both of the detectors (114,116) detects its corresponding portion of the sequence.

US Patent:

48948470, Jan 16, 1990

Filed:

May 26, 1987

Appl. No.:

7/054419

Inventors:

Taruna Tjahjadi - Duluth GA
German E. Correa - Alpharetta GA
Matthew F. Easley - Lilburn GA
John N. Martin - Atlanta GA
Charles H. McCorvey - Dunwoody GA
Randy D. Nash - Dacula GA
Cynthia A. Panella - Alpharetta GA
Michael L. Rubinstein - Atlanta GA
Martin H. Sauser - Atlanta GA
David F. Strawn - Marietta GA
George R. Thomas - Marietta GA

Assignee:

Hayes Microcomputer Products, Inc. - Norcross GA

International Classification:

H04L 2300

US Classification:

375121

Abstract:

A modem with improved signal processing and handshaking capabilities as described. Two digital signal processors are used to perform independent, concurrent operations so that a faster execution rate is obtained and more precise calculations are made possible. The modem also uses an improved handshaking technique which allows the modem to maintain compatibility with existing 1200 and 2400 bps modems while allowing for negotiation for 4800 and 9600 bps communications. The modem also incorporates an improved baud clock recovery circuit which dynamically adjusts the actual sampling point in a manner dependent upon the difference between the actual sampling point and the optimal sampling point. This allows the actual sampling point to converge upon the desired sampling point at a high rate while minimizing jitter around the optimal sampling point.

US Patent:

50401947, Aug 13, 1991

Filed:

Feb 9, 1989

Appl. No.:

7/309209

Inventors:

Taruna Tjahjadi - Norcross GA
Randy D. Nash - Dacula GA

Assignee:

Hayes Microcomputer Products, Inc. - Norcross GA

International Classification:

H04L 2708

US Classification:

375 98

Abstract:

An improved circuit for providing automatic gain control (AGC) for incoming phase shift keyed (PSK) and quadrature amplitude modulated (QAM) signals. An absolute value circuit (193) and a comparator (195) provide a first error signal (197). An integrater (200,202) smoothes the first error signal (197) to provide a second error signal (201) to a variable-threshold threshold detector (204). The threshold (209) is initially set at a low value to allow the AGC circuit to quickly respond. A larger value is then used to reduce susceptibility to noise and provide for proper QAM operation. An error circuit (208,211,213) provides a non-linear response so that the gain variations will be small when the input signal (190) is large. This non-linear response further reduces the effects of noise on the AGC circuit.

US Patent:

49724363, Nov 20, 1990

Filed:

Oct 14, 1988

Appl. No.:

7/257733

Inventors:

Raouf Y. Halim - Alpharetta GA
Randy D. Nash - Dacula GA

Assignee:

Hayes Microcomputer Products, Inc. - Norcross GA

International Classification:

H04B 1406

US Classification:

375 28

Abstract:

An improved analog front end circuit for a high performance modem comprising an oversampling sigma delta modulator analog-to-digital converter which employs a novel four phase clocked MOSFET switched capacitor integrator. The integrator is switched in a manner as to eliminate signal dependent charges in the MOSFET switches. The sigma delta modulator shifts quantization noise of the analog-to-digital conversion process out of baseband of the analog signal. A novel integrated decimating FIR low pass filter filters the quantization noise from the digital output signals, and reduces the number of digital signals to obtain a sufficient number of signal samples in order to provide operation at high speeds, for example 9600 bps. The improved four phase switched capacitor integrator is also suitable for use in sigma delta modulator circuits, analog-to-digital converter circuits, integrating cirucits, and the like. A novel return-to-zero circuit eliminates distortion in a sigma delta modulator based analog-to-digital conversion process which can result from unequal rise and fall times of the digital output, by insuring that the energies in signals represented by a "one" and signals represented by a "zero" are equal, even during portions of the bit stream wherein there is a consecutive sequence of "ones".

US Patent:

49104748, Mar 20, 1990

Filed:

Feb 9, 1989

Appl. No.:

7/308815

Inventors:

Taruna Tjahjadi - Duluth GA
Randy D. Nash - Dacula GA
Steven R. Sweitzer - Hillsborough CA

Assignee:

Hayes Microcomputer Products, Inc. - Norcross GA

International Classification:

H03C 500
H03K 710

US Classification:

332103

Abstract:

An improved circuit for generating phase and amplitude modulated signals in a modem. A first circuit (161) generates a first signal (163) using a 1200 Hz carrier (160) and an input data stream (162). This signal (163) is generated at the rate of 7200 samples per second. The first signal (163) is then sampled by a sampler (164) at a 3600 Hz rate (165). The sampled signal (166) contains both a 1200 Hz signal and a 2400 Hz signal. A bandpass filter (43) selects a 1200 Hz or a 2400 Hz center frequency. The resulting output (44) is a selectable 1200 Hz or 2400 Hz signal which is generated using only the data sampling points necessary to generate the first, 1200 Hz signal (163).

US Patent:

48497037, Jul 18, 1989

Filed:

Apr 1, 1988

Appl. No.:

7/176692

Inventors:

Matthew F. Easley - Decatur GA
German E. Correa - Marietta GA
Randy D. Nash - Dacula GA
Cynthia A. Panella - Alpharetta GA
Taruna Tjahjadi - Norcross GA

Assignee:

Hayes Microcomputer Products, Inc. - Norcross GA

International Classification:

H03K 117
H03K 700

US Classification:

328 63

Abstract:

An improved baud clock recovery, synchronization and data sampling circuit for a modem. A CODEC (41) samples the incoming signal at a rate determined by the sample clock output of a presettable counter (236). The sampled signal is then squared (231) and bandpass filtered (232) to provide a recovered baud clock. A detector (233) signals the positive going zero-crossing points of the recovered baud clock. A lead/lag calculator (234) determines which of the signal samples is nearest the zero-crossing point. The calculator (234) then determines whether this and every subsequent 12th sampling point leads or lags the zero-crossing point by inspecting the sign of the recovered baud clock and adjusts the preset inputs of the counter (236) to cause the sample points to occur at the zero-crossing point.