Randy N Siade

US Patent:

6919718, Jul 19, 2005

Filed:

Nov 10, 2003

Appl. No.:

10/705369

Inventors:

Randy Neaman Siade - Chandler AZ, US
Terry Sinclair Connacher - Scottsdale AZ, US
James Vernon Rhodes - Chandler AZ, US
James Mason Brafford - Mission Viejo CA, US
John Charles Montgomery - Poway CA, US
David Jon Mortensen - Mission Viejo CA, US

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R001/04
G01R031/26

US Classification:

3241581, 324765

Abstract:

An electromechanical system for testing IC-chips includes a chip holding subassembly which has sockets for holding a group of IC-modules that include the IC-chips; a moving mechanism for automatically moving the chip holding subassembly from a load position in the system to a test position in the system, and visa-versa; a temperature control mechanism which contacts the IC-modules on the chip holding subassembly only when that subassembly is at the test position; and a chip handler mechanism for automatically moving the IC-modules into and out of the sockets, when the chip holding subassembly is at the load position. At the test position, the temperature control mechanism contacts the IC-modules to control their temperature. At the load position, the chip handler mechanism automatically unloads one group of IC-modules from the sockets on the chip holding subassembly and automatically loads another group of the IC-modules into the sockets.

US Patent:

6924636, Aug 2, 2005

Filed:

Nov 10, 2003

Appl. No.:

10/705524

Inventors:

Randy Neaman Siade - Chandler AZ, US
Terry Sinclair Connacher - Scottsdale AZ, US
James Vernon Rhodes - Chandler AZ, US
James Mason Brafford - Mission Viejo CA, US
John Charles Montgomery - Poway CA, US
David Jon Mortensen - Mission Viejo CA, US

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R001/04
G01R031/26

US Classification:

3241581, 324765

Abstract:

An electromechanical system for testing IC-chips includes a total of N chip holding subassemblies, where N is an integer greater than one and where each chip holding subassembly has sockets for holding a group of IC-modules that include the IC-chips; a moving mechanism for automatically moving the i-th chip holding subassembly from a load position in the system to a test position in the system, and visa-versa, where i ranges from 1 to N and changes with time in a sequence; and a temperature control mechanism which contacts the IC-modules at the test position. Between the moving of the i-th chip holding subassembly and the next chip holding subassembly in the sequence, the IC-chips are burn-in tested on all N of the chip holding subassemblies. Also, while the i-th chip holding subassembly is being moved, burn-in testing of IC-chips on the remaining N-1 chip holding subassemblies continues.

US Patent:

7355386, Apr 8, 2008

Filed:

Nov 18, 2005

Appl. No.:

11/282209

Inventors:

Randy Neaman Siade - Chandler AZ, US
James Mason Brafford - Mission Viejo CA, US
James Downie - Mission Viejo CA, US

Assignee:

Delta Design, Inc. - Poway CA

International Classification:

G01R 31/26

US Classification:

3241581, 324765

Abstract:

A method of automatically carrying IC-chips, on a planar array of vacuum nozzles, to a variable target in a chip tester uses a set of laser distance sensors to align the vacuum nozzles with the target. Alignment occurs when certain combinations of distance and distance changes are sensed.

US Patent:

6909299, Jun 21, 2005

Filed:

Nov 10, 2003

Appl. No.:

10/705368

Inventors:

Randy Neaman Siade - Chandler AZ, US
Terry Sinclair Connacher - Scottsdale AZ, US
James Vernon Rhodes - Chandler AZ, US
James Mason Brafford - Mission Viejo CA, US
John Charles Montgomery - Poway CA, US
David Jon Mortensen - Mission Viejo CA, US

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R031/02

US Classification:

324755, 324760

Abstract:

An electromechanical system for testing IC-chips includes a total of N chip holding subassemblies; a moving mechanism for automatically moving the i-th chip holding subassembly from a load position in the system to the test position in the systems, and visa-versa, where i ranges from 1 to N and changes with time in a sequence; and a signal generator which sends test signals to the IC-chips at the test position. Between the moving of the i-th chip holding subassembly and the next subassembly in the sequence, test signals are sent to the IC-chips on all N of the chip holding subassemblies such that the signals are shifted in time from one subassembly to another. Also, while the i-th chip holding subassembly is being moved, the time shifted test signals continue to be sent to the IC-chips on the remaining N−1 chip holding subassemblies.