Ranjit Joseph Rozario

US Patent:

6345328, Feb 5, 2002

Filed:

Jun 9, 1999

Appl. No.:

09/328940

Inventors:

Ranjit J. Rozario - San Jose CA
Sridhar P. Subramanian - Sunnyvale CA
Ravikrishna Cherukuri - Milpitas CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1314

US Classification:

710 52, 710 65, 710 70, 713600, 327144, 326 93

Abstract:

A gear box module or circuit can act as an interface for transferring data from a first clock domain to a second clock domain. The gear box circuit uses a level sensitive memory element coupled to an input selection circuit to receive data from logic in the first clock domain and provide the data to logic in the second clock domain. An input selection signal causes the selection circuit to select the input source for the level sensitive memory element, thereby allowing the proper signal to be provided as output to logic in the second clock domain. Additionally, the gear box can provide the proper output signal for logic in the second domain using circuitry to alternately mask the gear box output. The gear box receives control signals, including for example the input selection signal, from control circuitry. The logic in each clock domain does not have to be aware of the clock frequency on the other side of the gear box, nor does it need to be aware of the ratio of clock frequencies between clock domains.

US Patent:

6618793, Sep 9, 2003

Filed:

Dec 18, 2000

Appl. No.:

09/740670

Inventors:

Ranjit J. Rozario - San Jose CA
Ravikrishna Cherukuri - San Jose CA

Assignee:

Redback Networks, Inc. - San Jose CA

International Classification:

G06F 1202

US Classification:

711133, 711 3, 711100, 711118, 711154

Abstract:

Free memory can be managed by creating a free list having entries with address of free memory location. A portion of this free list can then be cached in a cache that includes an upper threshold and a lower threshold. Additionally, a plurality of free lists are created for a plurality of memory banks in a plurality of memory channels. A free list is created for each memory bank in each memory channel. Entries from these free lists are written to a global cache. The entries written to the global cache are distributed between the memory channels and memory banks.

US Patent:

6961822, Nov 1, 2005

Filed:

Aug 27, 2003

Appl. No.:

10/650317

Inventors:

Ranjit J. Rozario - San Jose CA, US
Ravikrishna Cherukuri - San Jose CA, US

Assignee:

Redback Networks Inc. - San Jose CA

International Classification:

G06F012/02

US Classification:

711133, 711 3, 711100, 711118, 711154

Abstract:

Free memory can be managed by creating a free list having entries with address of free memory location. A portion of this free list can then be cached in a cache that includes an upper threshold and a lower threshold. Additionally, a plurality of free lists are created for a plurality of memory banks in a plurality of memory channels. A free list is created for each memory bank in each memory channel. Entries from these free lists are written to a global cache. The entries written to the global cache are distributed between the memory channels and memory banks.

US Patent:

7206310, Apr 17, 2007

Filed:

Dec 28, 2001

Appl. No.:

10/032729

Inventors:

Edmund G. Chen - Sunnyvale CA, US
Ranjit Rozario - San Jose CA, US
Ravikrishna Cherukuri - Pleasanton CA, US

Assignee:

Redback Networks Inc. - San Jose CA

International Classification:

H04L 12/56
H04L 12/54

US Classification:

370389, 370428, 711100

Abstract:

A method and apparatus for replicating packet data within a network element are described herein. In one embodiment, a method includes storing packet data within a storage element, maintaining a transmit count value of the storage element, determining a release count value of the storage element, comparing the transmit count value and the release count value, and de-allocating the storage element in response to comparing the transmit count value and the release count value.

US Patent:

7254651, Aug 7, 2007

Filed:

Dec 18, 2000

Appl. No.:

09/740669

Inventors:

Ranjit J. Rozario - San Jose CA, US
Ravikrishna Cherukuri - San Jose CA, US

Assignee:

Redback Networks Inc. - San Jose CA

International Classification:

G06F 3/00

US Classification:

710 22, 710 23, 710 28, 710 5, 710 6, 710 52, 710 54

Abstract:

A scheduler configured to schedule multiple channels of a Direct Memory Access (DMA) device includes a shift structure having entries corresponding to the multiple channels to be scheduled. Each entry in the shift structure includes multiple fields. Each entry also includes a weight that is determined based on these multiple fields. The scheduler also includes a comparison-logic circuit that is configured to then sort the entries based on their respective weights.

US Patent:

7352748, Apr 1, 2008

Filed:

Nov 12, 2002

Appl. No.:

10/291999

Inventors:

Ranjit Rozario - San Jose CA, US
Gary S. Delp - Rochester MN, US

Assignee:

Redback Networks Inc. - San Jose CA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370392, 370420

Abstract:

In one embodiment, an apparatus comprises a logic coupled to receive a number of data packets. The logic comprises an execution unit to generate a request for routing data for a data packet of the number of data packets. The logic also includes a memory lookup engine coupled to the execution unit and a local memory. The local memory is to store routing data for the number of data packets. The memory lookup engine is to receive the request and to update the local memory upon determining that the routing data for the data packet is not found in the local memory. Additionally, the logic includes a communication logic coupled to the memory lookup engine. The communication logic is to transmit an update message to a remote logic. The update message is to cause the remote logic to update a remote memory, wherein the update message is transmitted based on a low priority update upon determining that a buffer for update messages of the remote memory is full when the local memory is updated.

US Patent:

7986706, Jul 26, 2011

Filed:

Apr 29, 2009

Appl. No.:

12/432373

Inventors:

Thomas C. Yip - Los Gatos CA, US
Michael Feng - Sunnyvale CA, US
Sun Den Chen - San Jose CA, US
Stephen Chow - Monte Sereno CA, US
Edward Ho - Fremont CA, US
Patrick Wang - Palo Alto CA, US
Srivi Dhruvanarayan - Cupertino CA, US
Ranjit Rozario - San Jose CA, US
Edmund Chen - Sunnyvale CA, US

Assignee:

Telefonaktiebolaget LM Ericsson - Stockholm

International Classification:

H04L 12/28

US Classification:

370412, 370410, 370411, 370413

Abstract:

A hierarchical pipelined distributed scheduling traffic manager includes multiple hierarchical levels to perform hierarchical winner selection and propagation in a pipeline including selecting and propagating winner queues of a lower level to subsequent levels to determine one final winning queue. The winner selection and propagation is performed in parallel between the levels to reduce the time required in selecting the final winning queue. In some embodiments, the hierarchical traffic manager is separated into multiple separate sliced hierarchical traffic managers to distributively process the traffic.

US Patent:

20120079228, Mar 29, 2012

Filed:

Sep 24, 2010

Appl. No.:

12/890479

Inventors:

EDMUND G. CHEN - SUNNYVALE CA, US
BRIAN ALLEYNE - LOS GATOS CA, US
ROBERT HATHAWAY - SUNNYVALE CA, US
RANJIT J. ROZARIO - SAN JOSE CA, US
TODD D. BASSO - SAN JOSE CA, US

International Classification:

G06F 12/00

US Classification:

711167, 711E12001

Abstract:

A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.