Raul J Garibay

US Patent:

20040054948, Mar 18, 2004

Filed:

Sep 17, 2002

Appl. No.:

10/244561

Inventors:

Teresa McLaurin - Dripping Springs TX, US
Peter Harrod - Cambridge, GB
Raul Garibay - Austin TX, US

Assignee:

ARM LIMITED

International Classification:

G01R031/28

US Classification:

714/726000

Abstract:

Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain such that it may be validated that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, such as a system-on-chip design.

US Patent:

20060085707, Apr 20, 2006

Filed:

Sep 28, 2004

Appl. No.:

10/952289

Inventors:

Waheed Khan - Austin TX, US
Raul Garibay - Austin TX, US
Denzil Fernandes - Austin TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/28

US Classification:

714726000

Abstract:

A system comprising a tester and an integrated circuit, where the integrated circuit comprises a flip-flop, the flip-flop coupled to the tester and a circuit logic. The flip-flop comprises a scan input signal and a scan output signal, the signals coupled to the tester. The flip-flop also comprises multiple clock input signals.

US Patent:

20060095732, May 4, 2006

Filed:

May 18, 2005

Appl. No.:

11/133870

Inventors:

Thang Tran - Austin TX, US
Raul Garibay - Austin TX, US
James Hardage - Austin TX, US

International Classification:

G06F 9/30

US Classification:

712217000

Abstract:

A method of instruction issue () in a microprocessor (, or ) with execution pipestages (E, E, etc.) and that executes a producer instruction Ip and issues a candidate instruction I() having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the candidate instruction Ias a function () of a pipestage EN(I) of first need by the candidate instruction for the source operand, a pipestage EA(Ip) of first availability of the destination operand from the producer instruction, and the one execution pipestage E(Ip) currently associated with the producer instruction. A method of data forwarding () in a microprocessor (, or ) having a pipeline () having pipestages (E, E, etc.), wherein the method includes scoreboarding information E(Ip) () to represent a changing pipestage position for data from a producer instruction Ip, and selectively forwarding () the data from the pipestage having the represented pipestage position E(Ip), based on the information (), to a receiving pipestage (, E) for a dependent instruction. Wireless communications devices (), systems, circuits, devices, scoreboards (N), processes and methods of operation, processes and articles of manufacture (FIGS. -), are also disclosed.

US Patent:

20060271738, Nov 30, 2006

Filed:

May 24, 2005

Appl. No.:

11/136169

Inventors:

Thang Tran - Austin TX, US
Raul Garibay - Austin TX, US
Muralidharan Chinnakonda - Austin TX, US
Paul Miller - Dripping Springs TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 12/00

US Classification:

711122000

Abstract:

A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.

US Patent:

20070028051, Feb 1, 2007

Filed:

Aug 1, 2005

Appl. No.:

11/193633

Inventors:

Barry Williamson - Cedar Park TX, US
Gerard Williams - Sunset Valley TX, US
Muralidharan Chinnakonda - Austin TX, US
Raul Garibay - Austin TX, US

Assignee:

ARM Limited - Cambridge
Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 12/00

US Classification:

711128000, 711216000

Abstract:

The application discloses a data processor operable to process data, said data processor comprising: a cache having a data item storage location identified by an address; a hash value generator operable to generate a hash value from at least some of said bits of said address said hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to a plurality of storage locations within said cache; wherein in response to a request to access said data item storage location said data processor is operable to compare a hash value generated from said address with at least some of said plurality of hash values stored within said buffer. The comparison providing an indication of the storage location of the data item.

US Patent:

20220276983, Sep 1, 2022

Filed:

May 16, 2022

Appl. No.:

17/745742

Inventors:

- Austin TX, US
Malav Parikh - Austin TX, US
Paul Toth - Austin TX, US
Adam Caughron - Austin TX, US
Vimal Reddy - Austin TX, US
Erik Schlanger - Austin TX, US
Sergio Schuler - Austin TX, US
Zainab Nasreen Zaidi - Austin TX, US
Alex Dang-Tran - Austin TX, US
Raul Garibay - Austin TX, US
Bryant Sorensen - Austin TX, US

International Classification:

G06F 15/78
G06F 15/173
G06F 17/16
H04L 45/00
G06F 9/38

Abstract:

A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.

US Patent:

20210157648, May 27, 2021

Filed:

Nov 24, 2020

Appl. No.:

17/102643

Inventors:

- Austin TX, US
Sergio Schuler - Austin TX, US
Vimal Reddy - Austin TX, US
Zainab Zaidi - Austin TX, US
Paul Toth - Austin TX, US
Adam Caughron - Austin TX, US
Bryant Sorensen - Austin TX, US
Alexander Dang-Tran - Austin TX, US
Scott Johnson - Austin TX, US
Raul Garibay - Austin TX, US
Andrew Morten - Austin TX, US
David Fick - Cedar Park TX, US

International Classification:

G06F 9/50
G06N 3/04
G06F 9/48

Abstract:

A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.

US Patent:

20200192858, Jun 18, 2020

Filed:

Feb 13, 2020

Appl. No.:

16/790240

Inventors:

- Austin TX, US
Malav Parikh - Austin TX, US
Paul Toth - Austin TX, US
Adam Caughron - Austin TX, US
Vimal Reddy - Austin TX, US
Erik Schlanger - Austin TX, US
Sergio Schuler - Austin TX, US
Zainab Nasreen Zaidi - Austin TX, US
Alex Dang-Tran - Austin TX, US
Raul Garibay - Austin TX, US
Bryant Sorensen - Austin TX, US

International Classification:

G06F 15/173
G06F 15/78
G06F 17/16
G06F 9/38

Abstract:

A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.