Ravi J Gupta

US Patent:

7835467, Nov 16, 2010

Filed:

Jan 5, 2006

Appl. No.:

11/325804

Inventors:

Ravi Gupta - Sunnyvale CA, US

Assignee:

Qualcomm, Incorporated - San Diego CA

International Classification:

H04L 27/06

US Classification:

375319, 375346

Abstract:

A DC voltage offset correction circuit that provides for correction of a DC offset voltage of an output of a filter stage of a complex filter circuit includes a DC offset sensing device that is connected to an output of a filter stage of a complex filter to generate an offset presence signal indicating presence of the DC offset voltage at the output of the filter stage. The digital-to-analog converter applies a compensation signal to the output conditional on the offset presence signal. A programming register receives the offset presence signal to perform a binary search to generate a digital signal to force the digital-to-analog converter to apply the compensation voltage to the output of the filter stage. A filter controller sets the compensation voltage level in the programming register to match a programmed gain value of the filter stage.

US Patent:

7844937, Nov 30, 2010

Filed:

Dec 6, 2007

Appl. No.:

11/951558

Inventors:

Arvind Raman - Austin TX, US
Ravi Gupta - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

716 18

Abstract:

A processor-implemented method for making a semiconductor device having a test logic block and a functional logic block is provided. The method includes retrieving hardware description for at least one test logic block and mapping the hardware description for the at least one test logic block to logic gates to generate at least one synthesized test logic block. The method further comprises retrieving hardware description for at least one functional logic block and mapping the hardware description for the at least one functional logic block to logic gates to generate at least one synthesized functional logic block. The method further includes merging the at least one synthesized test logic block with the at least one synthesized functional logic block when the at least one functional logic block meets at least one criterion for selection as a candidate for merger with the at least one test logic block.

US Patent:

8189408, May 29, 2012

Filed:

Nov 17, 2009

Appl. No.:

12/620314

Inventors:

Ravi Gupta - Austin TX, US
David R. Bearden - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 7/00

US Classification:

36518912, 36518917, 36523005

Abstract:

An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.

US Patent:

20070207490, Sep 6, 2007

Filed:

Mar 6, 2007

Appl. No.:

11/714408

Inventors:

Jacquelyn Benfield - San Francisco CA, US
Ravi Gupta - Foster City CA, US
Ralph Jocham - San Jose CA, US
Pui-Ling Lam - Pacifica CA, US

Assignee:

Applera Corporation - Foster City CA

International Classification:

C12Q 1/68
G06F 19/00
C12M 3/00

US Classification:

435006000, 435287200, 702020000

Abstract:

Systems and methods are provided that relate to a platform, techniques, and processes for verifying the precision, sensitivity, accuracy, reproducibility, and other characteristics of biological tests, such as DNA identification or other tests or assays. According to various embodiments, a logic engine can guide a user to arrange, conduct, and record studies designed to ensure that chemistry kits and laboratory operations return dependably valid results. The validation platform can manage the design of the entire validation workflow, from initiation of a verification project for one or more chemistry kits or other assays or equipment, to design of individual studies to test the accuracy, sensitivity, reproducibility, and other parameters of biological testing. The validation engine can automatically generate a sample plate layout to conduct individual assays. The validation engine can likewise automatically generate unified data output recording the studies which were undertaken, the assays used, tests results, and other data.

US Patent:

20070245184, Oct 18, 2007

Filed:

Mar 6, 2007

Appl. No.:

11/714409

Inventors:

Jacquelyn Benfield - San Francisco CA, US
Ravi Gupta - Foster City CA, US
Ralph Jocham - San Jose CA, US
Pui-Ling Lam - Pacifica CA, US

Assignee:

Applera Corporation - Foster City CA

International Classification:

G01R 31/28

US Classification:

714724000

Abstract:

Systems and methods are provided that relate to a platform, techniques, and processes for verifying the precision, sensitivity, accuracy, reproducibility, and other characteristics of biological tests, such as DNA identification or other tests or assays. According to various embodiments, a logic engine can guide a user to, arrange, conduct, and record studies designed to ensure that chemistry kits and laboratory operations return dependably valid results. The validation platform can manage the design of the entire validation workflow, from initiation of a verification project for one or more chemistry kits or other assays or equipment, to design of individual studies to test the accuracy, sensitivity, reproducibility, and other parameters of biological testing. The validation engine can automatically generate a sample plate layout to conduct individual assays. The validation engine can likewise automatically generate unified data output recording the studies which were undertaken, the assays used, tests results, and other data.

US Patent:

20080209283, Aug 28, 2008

Filed:

Feb 23, 2007

Appl. No.:

11/678258

Inventors:

Ravi Gupta - Austin TX, US
Robert L. Bailey - Austin TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

G11C 29/00

US Classification:

714718, 365201

Abstract:

A memory device includes a latch component including a first input configured to receive a functional data bit associated with a functional operation, a second input configured to receive a memory test/repair data bit associated with a memory test operation, and a latch comprising a data input and a data output and select logic configured to selectively connect one of the first input or the second input to the data input of the latch based on a mode of operation of the memory device. A method includes operating a memory device in a first mode associated with a memory test operation and in a second mode associated with a functional operation. The method further includes storing a memory test/repair data bit at a latch component of the memory device in the first mode and storing a functional data bit at the latch component in the second mode.

US Patent:

20090226916, Sep 10, 2009

Filed:

Feb 2, 2009

Appl. No.:

12/364447

Inventors:

Bruce E. DeSimas - Danville CA, US
Ravi Gupta - Foster City CA, US
Lisa M. Calandro - San Ramon CA, US

Assignee:

Life Technologies Corporation - Carlsbad CA

International Classification:

C12Q 1/68
C12M 1/34

US Classification:

435 6, 4352872

Abstract:

The present invention provides a system and methods for deconvoluting mixed DNA samples. Applications developed according to the invention may be used for resolving two or more person mixtures into easy to interpret contributor profiles and to perform automated statistical calculations. An automated analysis approach for mixed samples integrating hardware and software functionalities providing enhanced user convenience and functionality is also provided.

US Patent:

20130103951, Apr 25, 2013

Filed:

Aug 23, 2012

Appl. No.:

13/593318

Inventors:

Leonard Klevan - Orinda CA, US
Hugh Pasika - San Francisco CA, US
Ravi Gupta - Foster City CA, US
Allan Minn - , US
Phillip McClurg - , US

Assignee:

LIFE TECHNOLOGIES CORPORATION - Carlsbad CA

International Classification:

H04L 9/32

US Classification:

713186

Abstract:

The present application relates to systems and methods using biometric data of an individual for identifying the individual and/or verifying the identity of an individual. These systems and methods are useful for, amongst many applications, more secure identification of high-risk individuals attempting to gain access to an entity, transport, information, location, security organization, law enforcement organization, transaction, services, authorized status, and/or funds.