Ravi A Nanavati

US Patent:

7665059, Feb 16, 2010

Filed:

Jun 7, 2006

Appl. No.:

11/448582

Inventors:

Edward W. Czeck - Winchester MA, US
Ravi A. Nanavati - Brighton MA, US
Rishiyur S. Nikhil - Arlington MA, US
Joseph E. Stoy - Boston MA, US

Assignee:

Bluespec, Inc. - Waltham MA

International Classification:

G06F 17/50

US Classification:

716 18, 717140, 716 1, 716 6

Abstract:

A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.

US Patent:

8572534, Oct 29, 2013

Filed:

Feb 16, 2010

Appl. No.:

12/706470

Inventors:

Edward W. Czeck - Winchester MA, US
Ravi A. Nanavati - Brighton MA, US
Rishiyur S. Nikhil - Arlington MA, US
Joseph E. Stoy - Boston MA, US

Assignee:

Bluespec, Inc. - Framingham MA

International Classification:

G06F 9/455
G06F 17/50

US Classification:

716113, 716106, 716108, 716110, 716112

Abstract:

A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.

US Patent:

7647567, Jan 12, 2010

Filed:

Jan 31, 2005

Appl. No.:

11/047329

Inventors:

Thomas M. Esposito - Medford MA, US
Mieszko Lis - Cambridge MA, US
Ravi A. Nanavati - Brighton MA, US
Joseph E. Stoy - Boston MA, US
Jacob B. Schwartz - Somerville MA, US

Assignee:

Bluespec, Inc. - Waltham MA

International Classification:

G06F 9/45
G06F 17/50

US Classification:

716 2, 716 4, 716 5

Abstract:

A system and method for Term Rewriting System hardware design employs a scheduler that incorporates a preference order in scheduling conflicting rules. The scheduler schedules a conflicting rule to execute when its predicate is true, and it is preferred over other conflicting rules in the preference order. The preference order may be, in one embodiment, a user-specified preference order enumerated by a designer. Such an order may be chosen according to efficiency criteria, such that the conflicting rule most essential for efficient hardware will be scheduled to execute on a given state rather than less essential conflicting rules The system and method advantageously permits a schedule to be computed in a time frame polynomially related to the number of rules, and produces more predictable and more easily understood schedules than conventional methods.