Ray D Sundstrom

US Patent:

54443954, Aug 22, 1995

Filed:

Dec 6, 1993

Appl. No.:

8/161559

Inventors:

Dwight D. Esgar - Mesa AZ
Ray D. Sundstrom - Chandler AZ
Phuc C. Pham - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 190175
H03K 1704

US Classification:

326 73

Abstract:

A non-saturating transistor circuit (11) having a first terminal (13), a control terminal (12), and a second terminal (14). The first terminal (13), control terminal (12), and second terminal (14) correspond respectively to a collector, base, and emitter of a transistor. The non-saturating transistor circuit (11) comprises a voltage divider (15), a diode (19), and a transistor (16). The voltage divider (15) enables the transistor (16) when a voltage is applied across the control terminal (12) and the second terminal (14) of non-saturating transistor circuit (11). The diode (19) removes current drive to the transistor (16) prior to the transistor (16) becoming saturated thus preventing the transistor (16) from saturating under all operating conditions.

US Patent:

54345235, Jul 18, 1995

Filed:

Apr 5, 1994

Appl. No.:

8/223186

Inventors:

Ray D. Sundstrom - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 3017

US Classification:

327172

Abstract:

The present invention provides an output signal whose pulse width may be adjusted with respect to the pulse width of an incoming input signal. In particular, a plurality of signals is generated in response to the input signal. One of the plurality of signals is selected for controlling when the output signal transitions from a first logic state to a second logic state, and one of the plurality of signals is selected for controlling when the output signal transitions from a second logic state to a first logic state wherein the output signal has a pulse width being a function of the selection of the plurality of signals.

US Patent:

49946900, Feb 19, 1991

Filed:

Jan 29, 1990

Appl. No.:

7/471581

Inventors:

Ray D. Sundstrom - Chandler AZ
Cleon Petty - Tempe AZ
Dwight D. Esgar - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 19003

US Classification:

307443

Abstract:

A split level differential bus having first and second signals at first and second lines, respectively, for transmitting data from a typical driver to a typical receiver, includes a first independent voltage source for terminating the first line and a second independent voltage source for terminating the second line, the second independent voltage source providing a voltage level that is different from the voltage level provided by the first independent voltage source. A current switch circuit controlled by the driver for switching current from the first line to the second line. A level shifting circuit coupled between the first line and the receiver for level shifting the first signal by a predetermined voltage.

US Patent:

49980297, Mar 5, 1991

Filed:

Jul 3, 1989

Appl. No.:

7/374722

Inventors:

Ray D. Sundstrom - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 19086
H03B 104

US Classification:

307475

Abstract:

An ECL to TTL translator converts a signal from ECL logic levels to TTL compatible logic levels without introducing current spikes in the output signal during logic translations. The ECL input signal is transformed into first and second differentially related currents which develop first and second voltages for biasing first and second switching circuits which in turn generate first and second complementary control signals. The sum total of the differentially related currents are limited to a predetermined magnitude blocking simultaneously assertion of the control signals. An output stage includes an upper and lower transistors each responsive to the first and second control signal respectively for developing a TTL high and TTL low output signal. The first and second switching circuits inhibit simultaneous conduction of the upper and lower transistors of the output stage preventing undesirable current spikes in the output signal thereof.

US Patent:

53941080, Feb 28, 1995

Filed:

Aug 31, 1992

Appl. No.:

7/937034

Inventors:

Ray D. Sundstrom - Chandler AZ

Assignee:

Motorola - Schaumburg IL

International Classification:

G06G 718

US Classification:

327335

Abstract:

Binary current signals are differentiated to produce pulses indicative of the front and rear edges. The pulses are amplified and utilized in a latch to regenerate binary voltage signals which are amplified replicas of the input signals. Because of the input differentiator the sensitivity of the circuit remains high while the latched output makes the circuit burst mode ready.

US Patent:

48148520, Mar 21, 1989

Filed:

Dec 7, 1987

Appl. No.:

7/129505

Inventors:

Ray D. Sundstrom - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2704
H01L 2986
H01L 2952

US Classification:

357 51

Abstract:

A diode having an increased diode voltage drop is provided through the use of an extra collector-base contact which is left electrically floating. By leaving the extra collector-base contact electrically floating, a voltage divider effect results which provides an increased voltage drop across the diode without requiring other structural changes nor increased diode current.

US Patent:

56731302, Sep 30, 1997

Filed:

Jan 2, 1996

Appl. No.:

8/582841

Inventors:

Ray D. Sundstrom - Chandler AZ
Daniel B. Schwartz - Apache Junction AZ
Stephen G. Shook - Gilbert AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 1000

US Classification:

359158

Abstract:

A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.

US Patent:

49805819, Dec 25, 1990

Filed:

May 21, 1990

Appl. No.:

7/526267

Inventors:

Dwight D. Esgar - Tempe AZ
Ray D. Sundstrom - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 19086

US Classification:

307473

Abstract:

A circuit having first and second inputs and first and second outputs includes a differential receiver circuit responsive to the first and second inputs for providing corresponding output logic signals at the first and second outputs. A tri-state detection circuit responsive to the first and second inputs and having an output for providing a first predetermined voltage to the differential receiver circuit when the first and second inputs are in a normal mode and for providing an increased second predetermined voltage to the differential receiver circuit when the first and second inputs are in a tri-state mode wherein oscillation of the differential receiver circuit is prevented and the outputs are forced to known logic states while the noise margin of the differential receiver is increased without a sacrifice in common mode range.