Raymond James Anderson

US Patent:

6564355, May 13, 2003

Filed:

Aug 30, 2000

Appl. No.:

09/651678

Inventors:

Larry D. Smith - San Jose CA
Raymond E. Anderson - Santa Cruz CA
Tanmoy Roy - Mountain View CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 4, 716 5, 716 6

Abstract:

A system and method for analyzing simultaneous switching noise. In one embodiment, a model may be provided for the electronic circuit to be analyzed. The electronic circuit may be an integrated circuit, a multi-chip module, a printed circuit assembly, or other type, and may in some embodiments include combinations of these types. The electronic circuit may include a plurality of drivers, each of which may be coupled to a power plane, a ground plane, and a transmission line. The connection of the driver may be accurately modeled in this manner. Each driver may be configured to switch between a logic high voltage and a logic low voltage. The modeled electronic circuit may also include a voltage source coupled to the power plane and the ground plane, a voltage regulator module, and a plurality of decoupling capacitors. The simultaneous switching of a plurality of drivers, from a logic high to a logic low, or vice versa, may be simulated. The system and method may then allow for the calculation of solutions for the transmission line and the power planes (as will be detailed below).

US Patent:

6937971, Aug 30, 2005

Filed:

Jul 25, 2000

Appl. No.:

09/625578

Inventors:

Larry D. Smith - San Jose CA, US
Raymond E. Anderson - Santa Cruz CA, US
Tanmoy Roy - Mountain View CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F017/50

US Classification:

703 18, 716 4, 716 5

Abstract:

A system and method for determining the desired decoupling components for a power distribution system having a voltage regulator module. The system may employ a mathematical model of a voltage regulator circuit, such as a switching voltage regulator. The mathematical model may be a SPICE model, or a circuit model in another format. The method may include simulating the operation of the power distribution system to obtain a estimate of the bulk capacitance required for effective decoupling. For digital systems, the method may include a cycle-by-cycle simulation of the power distribution system, wherein the simulation occurs over a number of clock cycles. The performance of the power distribution system may then be analyzed for each simulated clock cycle. The simulation may also include analyzing the transient responses and loop stability of the power distribution. Based on the results of these various simulations, the bulk capacitance value may be refined, thus allowing the system to begin the selection of specific decoupling components from the database in order to satisfy the bulk capacitance requirements.

US Patent:

61956139, Feb 27, 2001

Filed:

Sep 8, 1998

Appl. No.:

9/149164

Inventors:

Tanmoy Roy - Mountain View CA
Larry D. Smith - San Jose CA
Raymond E. Anderson - Santa Cruz CA
Thomas J. Pelc - Fremont CA
Douglas W. Forehand - Mountain View CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G01R 2700
H01G 4228

US Classification:

702 65

Abstract:

A system and method for measuring the equivalent series resistance (ESR) of one or more capacitors using an impedance analyzer, whereby the capacitors are joined to the impedance analyzer with a conductive adhesive. The conductive adhesive may advantageously provide for an electrically and mechanically stable connection between the capacitor and the remainder of the electrical circuit used to measure the ESR of the capacitor. The conductive adhesive may include heat activated or cold solder, or conductive putty. The system comprises a measuring unit for sweeping a frequency range to find the minimum impedance for the capacitor and a connector assembly for holding the capacitor in an electrically and mechanically stable connection using the conductive adhesive. The connector assembly includes a mating portion adapted for electrically connecting the connector assembly to an I/O port of the measuring unit and a terminal portion that accommodates a connection to the capacitor using the conductive adhesive. The method comprises connecting a mating portion of the connector assembly to the impedance analyzer.

US Patent:

20150222033, Aug 6, 2015

Filed:

Feb 6, 2014

Appl. No.:

14/174697

Inventors:

- San Jose CA, US
Sarajuddin Niazi - Union City CA, US
Raymond E. Anderson - Santa Cruz CA, US
Suresh Ramlingam - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01R 12/71
H01R 43/02

Abstract:

An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

Address:

13334 Black Cyn Dr, Austin, TX 78729

VIN:

1N4AL21EX7C207429

Make:

NISSAN

Model:

ALTIMA

Year:

2007