Raymond John Lim

US Patent:

6636952, Oct 21, 2003

Filed:

Jun 15, 2001

Appl. No.:

09/880873

Inventors:

Song Zhang - San Jose CA
Anurag P. Gupta - Saratoga CA
Raymond Lim - Mountain View CA
Jorge Cruz-Rios - Los Altos CA
Phil Lacroute - Sunnyvale CA

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

711154, 711137

Abstract:

A network device includes systems and methods for processes streams of data. The network device stores data and addresses corresponding to the streams in a memory. The addresses store pointers to the data. Output logic within the network device determines whether an address is required to be fetched. When no address is required to be fetched, then data is read from the memory. When an address is required to be fetched, the address is fetched from the memory and data is read from the memory using the fetched address. To facilitate this, notifications may be stored corresponding to the streams and notification pointers may be used to identify ones of the notifications to be processed. A prefetch pointer may also be used to identify a notification with one or more associated addresses to be prefetched.

US Patent:

6941433, Sep 6, 2005

Filed:

May 22, 2002

Appl. No.:

10/152006

Inventors:

Jeffrey G. Libby - Cupertino CA, US
Raymond M. Lim - Los Altos Hills CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F012/00

US Classification:

711167, 711115, 711147, 711154, 365191, 365194

Abstract:

A system for determining a memory read latency includes a memory, a memory read circuit, and a latency detector. An identifiable pattern of data is written to at least one location in the memory, and a read request and the address of the identified pattern are sent to the memory. The latency detector determines a read latency period based on detecting the identifiable pattern of data.

US Patent:

7158520, Jan 2, 2007

Filed:

Mar 22, 2002

Appl. No.:

10/102961

Inventors:

Pradeep Sindhu - Los Altos Hills CA, US
Raymond M. Lim - Los Altos Hills CA, US
Jeffrey G. Libby - Cupertino CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370392, 370352, 370353, 370401, 370389, 709213, 709214, 709215, 709231, 709232, 709238

Abstract:

A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. Mailbox registers allow the L2 and L3 header generation units to communicate with one another. The L2 header generation unit may write to a specified mailbox register only when a valid bit corresponding to the mailbox register indicates that the register does not contain valid data. After writing to the mailbox register, the L2 header generation unit changes the state of the valid bit. The L3 register then reads from the mailbox register and changes the state of the valid bit. A similar implementation of the mailbox registers allows data to flow from the L3 header generation unit to the L2 header generation unit.

US Patent:

7180893, Feb 20, 2007

Filed:

Mar 22, 2002

Appl. No.:

10/102960

Inventors:

Pradeep Sindhu - Los Altos Hills CA, US
Raymond M. Lim - Los Altos Hills CA, US
Jeffrey G. Libby - Cupertino CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/56
H04J 3/22
G06F 9/30

US Classification:

370392, 370469, 712212

Abstract:

A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When both the L2 and L3 generation units complete their operations for a particular packet, a build component combines the generated L2 and L3 header information from the buffers to form a complete packet header.

US Patent:

7212530, May 1, 2007

Filed:

Mar 22, 2002

Appl. No.:

10/102932

Inventors:

Raymond M. Lim - Los Altos Hills CA, US
Jeffrey G. Libby - Cupertino CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/56

US Classification:

370392, 370401

Abstract:

A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When the L2 and L3 header generation units finish processing a packet, the packet may be unloaded from the first and second buffer while a new packet is simultaneously loaded to the packet header processing engine.

US Patent:

7239630, Jul 3, 2007

Filed:

Mar 22, 2002

Appl. No.:

10/102931

Inventors:

Raymond M. Lim - Los Altos Hills CA, US
Jeffrey G. Libby - Cupertino CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/66

US Classification:

370353, 370392, 370352, 370401, 370389, 709236, 709230

Abstract:

A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit may include a single execution section and the L3 generation unit may include multiple parallel execution sections. When both the L2 and L3 generation units complete their operations on a particular packet, a build component combines the generated L2 and L3 information to form a complete packet header.

US Patent:

7289503, Oct 30, 2007

Filed:

Jul 30, 2002

Appl. No.:

10/206999

Inventors:

Pradeep Sindhu - Los Altos Hills CA, US
Debashis Basu - San Jose CA, US
Pankaj Patel - Cupertino CA, US
Raymond Lim - Los Altos Hills CA, US
Avanindra Godbole - San Jose CA, US
Tatao Chuang - San Jose CA, US
Chi-Chung K. Chen - Cupertino CA, US
Jeffrey G. Libby - Cupertino CA, US
Dennis Ferguson - Palo Alto CA, US
Philippe Lacroute - Sunnyvale CA, US
Gerald Cheung - Palo Alto CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/28

US Classification:

370392, 370432

Abstract:

A network device includes an interface and packet processing logic. The interface receives a multicast packet. The packet processing logic determines identifier data corresponding to the received multicast packet and replicates the identifier data to multiple outgoing packet forward engines at a first point in a processing path. The packet processing logic further replicates the identifier data to multiple data streams at a second point in the processing path and replicates the identifier data to multiple logical interfaces in the same stream at a third point in the processing path.

US Patent:

7292529, Nov 6, 2007

Filed:

Jul 31, 2002

Appl. No.:

10/208008

Inventors:

Debashis Basu - San Jose CA, US
Avanindra Godbole - San Jose CA, US
Raymond M. Lim - Los Altos Hills CA, US
Jeffrey Glenn Libby - Cupertino CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/26
H04L 12/54
H04L 12/56
H04J 3/24

US Classification:

370230, 370390, 370412, 370432, 370474

Abstract:

A system for multicasting a packet of data to a single data stream is provided. The system may determine a size of the packet and may send a single copy of the packet if the size of the packet exceeds a threshold value. A number of copies of the packet yet to be multicast may be ascertained if the size of the packet of data does not exceed the threshold value. Copies of the packet may be transmitted based on the number of copies of the packet yet to be multicast.