Raymond A Stevens

US Patent:

6381532, Apr 30, 2002

Filed:

Sep 20, 2000

Appl. No.:

09/665094

Inventors:

Gary T. Bastian - Colorado Springs CO
Kevin M. Rishavy - Colorado Springs CO
Martin G. Gravenstein - Nevada City CA
Robert L. Anderson - Saline MI
Rollie M. Fisher - Trenton MI
Raymond A. Stevens - Monument CO
Samuel J. Guido - Dearborn MI

Assignee:

Visteon Global Technologies, Inc. - Dearborn MI

International Classification:

G06F 1310

US Classification:

701114, 701115, 710 10, 710 19

Abstract:

An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

US Patent:

6427180, Jul 30, 2002

Filed:

Jun 22, 1999

Appl. No.:

09/337799

Inventors:

Gary Thomas Bastian - Colorado Springs CO
Kevin Michael Rishavy - Colorado Springs CO
Martin Gerard Gravenstein - Colorado Springs CO
Robert Lee Anderson - Saline MI
Rollie Morris Fisher - Trenton MI
Raymond Allen Stevens - Monument CO
Samuel James Guido - Dearborn MI

Assignee:

Visteon Global Technologies, Inc. - Dearborn MI

International Classification:

G06F 1300

US Classification:

710112, 710 5, 710 19, 701 48

Abstract:

A data queue control submodule supporting a host processor and at least one peripheral device. The submodule includes a memory unit with a first memory portion for storing queue commands associated with each peripheral device and a second memory portion for storing peripheral device data. A queue control unit is also included in the submodule for controlling the flow of data between the peripheral devices and the host processor in accordance with the queue control commands. A port interface connects the queue control unit and the peripheral devices in response to a trigger event. The submodule further includes an event controller in communication with the host processor and the port interface for generating event triggers in response to data demands of either the host processor or the other peripheral devices. The present invention is advantageous in that it simplifies the design of each port interface and provides improved flexibility in the queue structure of the overall control system.

US Patent:

6978340, Dec 20, 2005

Filed:

Jan 30, 2001

Appl. No.:

09/774230

Inventors:

Rollie M. Fisher - Trenton MI, US
Samuel J. Guido - Dearborn MI, US
Martin G. Gravenstein - Nevada City CA, US
Raymond A. Stevens - Monument CO, US

Assignee:

Visteon Corporation - Dearborn MI

International Classification:

G06F013/00

US Classification:

710316, 710317, 710 38, 370391

Abstract:

A controller has an I/O crossover switching network , an optional I/O network expansion , a plurality of serial I/O shifters , a clock generator and I/O control logic. The I/O crossover-switching network is also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA) or an optional alternate pathway which uses one of a plurality of parallel pins. The optional alternate pathway can be used when pins are unavailable or to reduce the number of pins on the device. The controller is shown to communicate with an external device also having parallel pins. While a single device is shown, the external device can be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessor of the present invention.

US Patent:

20180336149, Nov 22, 2018

Filed:

Oct 6, 2017

Appl. No.:

15/727561

Inventors:

- Norwood MA, US
Raymond Allen Stevens - Monument CO, US

International Classification:

G06F 13/362
G06F 13/42
G06F 11/07
G06F 1/32

Abstract:

Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence corresponds to the bit sequence of the event position, an event corresponding to the event position is enabled.