Rebecca Elizabeth Hebda

US Patent:

6374350, Apr 16, 2002

Filed:

Jun 1, 2000

Appl. No.:

09/584890

Inventors:

Reynold V. DSa - Portland OR
Rebecca E. Hebda - Sherwood OR
Stavros Kalafatis - Portland OR
Alan B. Kyker - Davis OR
Robert B. Chaput - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 942

US Classification:

712239, 712202, 712238

Abstract:

An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

US Patent:

6493821, Dec 10, 2002

Filed:

Jun 9, 1998

Appl. No.:

09/094027

Inventors:

Reynold V. DSa - Portland OR
Robert F. Krick - Beaverton OR
Rebecca E. Hebda - Sherwood OR
Alan B. Kyker - Portland OR

Assignee:

Intel Corporation - Hillsboro OR

International Classification:

G06F 938

US Classification:

712239, 712244, 714 15

Abstract:

A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch misprediction. The pipelined microprocessor further includes a decode stage which stores recovering state information for respective instructions and is responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event. The recovery state information may include, for example, a pointer to a next linear instruction, a pointer to a branch target instruction, a branch prediction, or an instruction source. Event recovery micro-code determines a next instruction to execute using the recovery state information, the next instruction being executed after a machine recovery.

US Patent:

7334115, Feb 19, 2008

Filed:

Jun 30, 2000

Appl. No.:

09/608512

Inventors:

Reynold V. D'Sa - Portland OR, US
Alan B. Kyker - Portland OR, US
Slade A. Morgan - Forest Grove OR, US
Rebecca E. Hebda - Sherwood OR, US
Richard A. Weier - Tigard OR, US
Robert F. Krick - Fort Collins CO, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/30

US Classification:

712239

Abstract:

The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.

US Patent:

7519799, Apr 14, 2009

Filed:

Nov 18, 2003

Appl. No.:

10/714674

Inventors:

Rebecca E. Hebda - Tigard OR, US
Jourdan J. Stephan - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

US Classification:

712245, 712211

Abstract:

Embodiments of the present invention relate to high-performance processors, and more specifically, to processors that store all operation information associated with each instruction in a single memory. A processor including multiple programmable logic arrays (PLAs); an instruction pointer queue coupled to the multiple PLAs; and an instruction pointer sequencing logic/predictor component coupled to the instruction pointer queue. The processor further includes a micro-operation cache coupled to the instruction pointer sequencing logic/predictor component; a micro-operation memory coupled to the micro-operation cache; and a trace pipe (TPIPE) coupled to the micro-operation cache and the instruction pointer queue.

US Patent:

60556307, Apr 25, 2000

Filed:

Apr 20, 1998

Appl. No.:

9/063205

Inventors:

Reynold V. D'Sa - Portland OR
Alan B. Kyker - Portland OR
Gad S. Sheaffer - Beaverton OR
Gustavo P. Espinosa - Portland OR
Stavros Kalafatis - Portland OR
Rebecca E. Hebda - Sherwood OR

Assignee:

Intel Corporation - Hillsboro OR

International Classification:

G06F 1314

US Classification:

712240

Abstract:

An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.

US Patent:

61516716, Nov 21, 2000

Filed:

Feb 20, 1998

Appl. No.:

9/027407

Inventors:

Reynold V. D'Sa - Portland OR
Rebecca E. Hebda - Sherwood OR
Stavros Kalafatis - Portland OR
Alan B. Kyker - Portland OR
Robert B. Chaput - Beaverton OR

Assignee:

Intel Corporation - Hillsboro OR

International Classification:

G06F 942

US Classification:

712239

Abstract:

An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.