Reginald Sia Yoong Young

US Patent:

20220366255, Nov 17, 2022

Filed:

Jul 27, 2022

Appl. No.:

17/874573

Inventors:

- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - San Jose CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US

International Classification:

G06N 3/08
G06F 15/80
G06N 3/063
G06N 5/04

Abstract:

A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

US Patent:

20210224654, Jul 22, 2021

Filed:

Apr 9, 2021

Appl. No.:

17/226256

Inventors:

- Mountain View CA, US
Reginald Clifford Young - Palo Alto CA, US

International Classification:

G06N 3/08
G06N 3/063
G06N 5/04

Abstract:

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a respective neural network output for each of a plurality of inputs, the method comprising, for each of the neural network layers: receiving a plurality of inputs to be processed at the neural network layer; forming one or more batches of inputs from the plurality of inputs, each batch having a number of inputs up to the respective batch size for the neural network layer; selecting a number of the one or more batches of inputs to process, where a count of the inputs in the number of the one or more batches is greater than or equal to the respective associated batch size of a subsequent layer in the sequence; and processing the number of the one or more batches of inputs to generate the respective neural network layer output.

US Patent:

20210209444, Jul 8, 2021

Filed:

Jan 14, 2021

Appl. No.:

17/149321

Inventors:

- Mountain View CA, US
Reginald Clifford Young - Palo Alto CA, US

International Classification:

G06N 3/04
G06F 17/16
G06N 3/063

Abstract:

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for depth concatenation using a matrix computation unit. One of the methods includes: receiving a request to process network inputs to a neural network using an integrated circuit, the neural network comprising a depth concatenation neural network layer; and generating instructions that, when executed by the integrated circuit, cause the integrated circuit to perform operations comprising: for each spatial location in a first input tensor to the depth concatenation layer and a second input tensor to the depth concatenation layer: multiplying, using the matrix computation unit, a second depth vector for the spatial location by a shift weight matrix for the depth concatenation layer to generate a shifted second depth vector; and adding the shifted second depth vector and a first input depth vector for the spatial location to generate a concatenated depth vector.

US Patent:

20210019618, Jan 21, 2021

Filed:

Jun 29, 2020

Appl. No.:

16/915161

Inventors:

- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US

International Classification:

G06N 3/08
G06F 15/80
G06N 3/063
G06N 5/04

Abstract:

A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

US Patent:

20200218981, Jul 9, 2020

Filed:

Mar 19, 2020

Appl. No.:

16/824411

Inventors:

- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US

International Classification:

G06N 3/08
G06N 5/04
G06N 3/063
G06F 15/80

Abstract:

A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

US Patent:

20200057942, Feb 20, 2020

Filed:

Oct 25, 2019

Appl. No.:

16/663876

Inventors:

- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US

International Classification:

G06N 3/08
G06N 5/04
G06N 3/063
G06F 15/80

Abstract:

A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

US Patent:

20190354834, Nov 21, 2019

Filed:

Aug 5, 2019

Appl. No.:

16/531774

Inventors:

- Mountain View CA, US
Reginald Clifford Young - Palo Alto CA, US

International Classification:

G06N 3/04
G06N 3/063
G06F 17/16

Abstract:

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for depth concatenation using a matrix computation unit. One of the methods includes: receiving a request to process network inputs to a neural network using an integrated circuit, the neural network comprising a depth concatenation neural network layer; and generating instructions that, when executed by the integrated circuit, cause the integrated circuit to performing operations comprising: for each spatial location in a first input tensor to the depth concatenation layer and a second input tensor to the depth concatenation layer: multiplying, using the matrix computation unit, a second depth vector for the spatial location by a shift weight matrix for the depth concatenation layer to generate a shifted second depth vector; and adding the shifted second depth vector and a first input depth vector for the spatial location to generate a concatenated depth vector.

US Patent:

20190354862, Nov 21, 2019

Filed:

Aug 1, 2019

Appl. No.:

16/529782

Inventors:

- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US

International Classification:

G06N 3/08
G06N 5/04
G06F 15/80
G06N 3/063

Abstract:

A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.