Renee S Garcia

US Patent:

20150108204, Apr 23, 2015

Filed:

Dec 23, 2014

Appl. No.:

14/581985

Inventors:

- Santa Clara CA, US
Sumit Kumar - Phoenix AZ, US
Sridhar Nara - San Jose CA, US
Renee D. Garcia - Gilbert AZ, US
Manohar S. Konchady - Chandler AZ, US
Suresh B. Yeruva - Chandler AZ, US
Lynn H. Chen - Gilbert AZ, US
Tyler N. Osborn - Gilbert AZ, US
Sairam Agraharam - Chandler AZ, US

International Classification:

H01L 23/00

US Classification:

22818022, 22818021

Abstract:

An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).