Richard Howell Bailey

US Patent:

7149137, Dec 12, 2006

Filed:

Dec 30, 2004

Appl. No.:

11/027221

Inventors:

John Anthony Rodriguez - Richardson TX, US
Richard Allen Bailey - Colorado Springs CO, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/00

US Classification:

365201, 365117, 365145, 365194

Abstract:

The present invention facilitates evaluation of ferroelectric memory devices. A ferroelectric memory device is fabricated that comprises memory cells comprising ferroelectric capacitors (). A short delay polarization value is obtained () by writing a data value, performing a short delay, and reading the data value. A long delay polarization value is obtained () by again writing the data value, performing a long delay, and again reading the data value. The short delay and long delay polarization values are compared () to obtain a data retention lifetime for the ferroelectric memory device. The obtained data retention lifetime is compared with acceptable values () and, if deemed unacceptable, avoids unnecessary performance of thermal bake data retention lifetime testing.

US Patent:

D562162, Feb 19, 2008

Filed:

Jul 11, 2006

Appl. No.:

29/262854

Inventors:

Albert Michael Forlenza - Carrollton TX, US
Samuel Edward Ivey - Richardson TX, US
Jerome F Krentel - Covington LA, US
John Eglin Williams - Covington LA, US
Joanne B. Haas - Covington LA, US
Paula A. Schweikert - Abita Springs LA, US
Kishore K. Kondabatni - Atlanta GA, US
Richard E. Bailey - Mandeville LA, US

Assignee:

Cimex Medical Innovations, L.C. - Covington LA

International Classification:

1004

US Classification:

D10 53

US Patent:

D562977, Feb 26, 2008

Filed:

Jul 11, 2006

Appl. No.:

29/262858

Inventors:

Albert Michael Forlenza - Carrollton TX, US
Samuel Edward Ivey - Richardson TX, US
Jerome F Krentel - Covington LA, US
John Eglin Williams - Covington LA, US
Joanne B. Haas - Covington LA, US
Paula A. Schweikert - Abita Springs LA, US
Kishore K. Kondabatni - Atlanta GA, US
Richard E. Bailey - Mandeville LA, US

Assignee:

Cimex Medical Innovations, L.C. - Covington LA

International Classification:

2402

US Classification:

D24133

US Patent:

D571472, Jun 17, 2008

Filed:

Jul 11, 2006

Appl. No.:

29/262863

Inventors:

Albert Michael Forlenza - Carrollton TX, US
Samuel Edward Ivey - Richardson TX, US
Jerome F Krentel - Covington LA, US
John Eglin Williams - Covington LA, US
Joanne B. Haas - Covington LA, US
Paula A. Schweikert - Abita Springs LA, US
Kishore K. Kondabatni - Atlanta GA, US
Richard E. Bailey - Mandeville LA, US

Assignee:

Cimex Medical Innovations, L.C. - Covington LA

International Classification:

2401

US Classification:

D24170

US Patent:

20190252016, Aug 15, 2019

Filed:

Apr 30, 2018

Appl. No.:

15/967511

Inventors:

- Dallas TX, US
Richard Allen Bailey - Richardson TX, US

International Classification:

G11C 11/22
H04L 9/32

Abstract:

A method of generating a random number from an electronic circuit memory and/or a system with the electronic circuit memory. The memory comprises a block of ferroelectric two transistor, two capacitor (2T-2C), memory cells. The method comprises: (i) first, writing a predetermined programming pattern to the block cells in a one transistor, one-capacitor (1T-1C) mode, thusly writing, per cell, a same data state to both a first and second sub-cell of the cell; (ii) second, reading the cells in a 2T-2C mode to generate a random number comprising a random bit from each of the cells; (iii) third, restoring the random number into the cells in a 2T-2C mode, thusly writing, per cell, a complementary data state to both a first and second sub-cell of the cell, responsive to a respective random number bit; and fourth, imprinting the random number in each cell in the block.

US Patent:

20180374861, Dec 27, 2018

Filed:

Aug 7, 2018

Appl. No.:

16/056827

Inventors:

- DALLAS TX, US
Richard Allen Bailey - Richardson TX, US
Antonio Guillemo Acosta - Richardson TX, US
John A. Rodriguez - Dallas TX, US
Scott Robert Summerfelt - Garland TX, US
Kemal Tamer San - Plano TX, US

International Classification:

H01L 27/11507
H01L 21/02
H01L 21/56
H01L 23/31
H01L 23/00

Abstract:

Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

US Patent:

20180188987, Jul 5, 2018

Filed:

Dec 22, 2017

Appl. No.:

15/852618

Inventors:

- Dallas TX, US
Robert C. Baumann - Dallas TX, US
Richard A. Bailey - Richardson TX, US

International Classification:

G06F 3/06
G06F 7/58
G11C 11/22

Abstract:

Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all 1's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

US Patent:

20180102184, Apr 12, 2018

Filed:

Dec 11, 2017

Appl. No.:

15/837451

Inventors:

- Dallas TX, US
John A. Rodriguez - Dallas TX, US
Richard A. Bailey - Richardson TX, US

International Classification:

G11C 29/50
G11C 11/22

Abstract:

A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.