Richard C Blish

US Patent:

6362524, Mar 26, 2002

Filed:

Jul 26, 2000

Appl. No.:

09/625367

Inventors:

Richard C. Blish - Saratoga CA
Kurt O. Taylor - San Jose CA
David C. Greenlaw - Dresden, DE

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257734, 257736, 257776, 257775, 438687

Abstract:

A metal edge seal ring is formed in a trench made up of a large number of short, connected legs in perpendicular relation. Metal is deposited in the trench, and because the metal is comprised of many short segments rather than several long, straight sections, the subsequent chemical-mechanical polishing step does not cause significant cupping of the metal in the trench.

US Patent:

6373126, Apr 16, 2002

Filed:

Apr 26, 2000

Appl. No.:

09/560253

Inventors:

Pramod Patel - San Jose CA
Richard C. Blish - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 23495

US Classification:

257666, 257676, 438123

Abstract:

Barrier structures are included within the packaging material of a packaged semiconductor device, such barrier structures including barrier bodies which overlie the die-die pad assembly of the device on either side thereof. The barrier bodies act as baffles which limit diffusion of moisture through the packaging material into the area of the die-die pad assembly of the device, the barrier bodies including apertures therethrough which control such diffusion in a manner that avoids delamination problems in the area of the die-die pad assembly, meanwhile also avoiding undesirable trapping of gas within the packaging material.

US Patent:

6395568, May 28, 2002

Filed:

Jul 25, 2000

Appl. No.:

09/624665

Inventors:

Richard C. Blish - Saratoga CA
Colin D. Hatchard - Campbell CA
Ian Morgan - San Jose CA
Michael Fliesler - Santa Cruz CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2166

US Classification:

438 17, 257252

Abstract:

Method for bond pad crater jeopardy identification in integrated circuits, and apparatus which performs the method. The gate or gates of a transistor or transistors of an ESD device are formed under each bond pad in the integrated circuit device. Connected to the transistor is circuitry for determimg the electrical, and hence mechanical, integrity of the transistor. A reduction in current through the transistor, by reason of microcrack formation in the several layers under the transistor causing a gate or gates of the transistor to crack and fail, may detected, Location of at least a portion of the ESD device, for example the above transistor, reduces overall chip area by increasing device density.

US Patent:

6483337, Nov 19, 2002

Filed:

Jul 26, 2000

Appl. No.:

09/625393

Inventors:

Richard C. Blish - Saratoga CA
Scott E. Johnson - Aptos CA

Assignee:

Advanced Micro Devices Inc. - Sunnyvale CA

International Classification:

G01R 3126

US Classification:

324765, 3241581, 324763, 714733

Abstract:

A semiconductor structure is tested for latchup characteristics by imposing increasing levels of current thereon, and measuring increase in structure current in response thereto. When an imposition in current results in a corresponding increase in semiconductor structure current which is not substantially linearly proportional to the amount of current imposed thereon, onset of latchup is indicated. Other semiconductor structures are tested, and measurements are compared to gain knowledge of the structures tested.

US Patent:

6548881, Apr 15, 2003

Filed:

Jul 25, 2000

Appl. No.:

09/624657

Inventors:

Richard C. Blish - Saratoga CA
Pramod D. Patel - San Jose CA
David E. Lewis - Sunnyvale CA
Colin D. Hatchard - Campbell CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2900

US Classification:

257499, 257 48

Abstract:

Method for stepping identification and bond pad crater jeopardy identification in integrated circuits and apparatus which performs the method, A unique device, a polysilicon meander, is formed under each bond pad in the integrated circuit device. Connected to the meander is circuitry for determining the electrical, and hence mechanical, integrity of the meander. Failure of the meander by reason of microcrack formation in the several layers under the meander is detected by the high resistance of the meander. The circuitry will also resolve any potential mismatch between the actual mask revision of the integrated circuit and the corresponding revision of the test program.

US Patent:

6751294, Jun 15, 2004

Filed:

Aug 8, 2002

Appl. No.:

10/215075

Inventors:

Richard C. Blish II - Saratoga CA
Susan Xia Li - Fremont CA
David S. Lehtonen - Austin TX
J. Courtney Black - San Jose CA
Don C. Darling - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G21K 300

US Classification:

378156, 2505051

Abstract:

An apparatus for x-raying a semiconductor device which includes semiconductor material and conductive material, the apparatus including a source of x-rays, a filter for receiving x-rays from the source of x-rays and allowing transmission of x-rays to the device, the filter having an atomic number greater than the atomic number of the conductive material of the device, and an x-ray imager for receiving x-rays from the device.

US Patent:

20070284748, Dec 13, 2007

Filed:

Jun 8, 2006

Appl. No.:

11/448788

Inventors:

Christy Woo - Cupertino CA, US
Jun "Charlie" Zhai - San Jose CA, US
Paul Besser - Sunnyvale CA, US
Kok-Yong Yiang - Sunnyvale CA, US
Richard C. Blish - Saratoga CA, US
Christine Hau-Riege - Fremont CA, US

International Classification:

H01L 23/52
H01L 23/48
H01L 29/40

US Classification:

257758

Abstract:

The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

US Patent:

20080102637, May 1, 2008

Filed:

Oct 31, 2006

Appl. No.:

11/590183

Inventors:

Jun Zhai - Sunnyvale CA, US
Richard C. Blish - Saratoga CA, US
Fei Wang - San Jose CA, US

International Classification:

H01L 21/311

US Classification:

438700

Abstract:

According to one exemplary embodiment, a method for characterizing a reliability of a semiconductor structure includes forming a recess in a first dielectric layer in the semiconductor structure; filling the recess with a sacrificial material; removing the sacrificial material thereby causing an intentional defect with known characteristics to aid in a characterizing the reliability of the semiconductor structure.