Richard R Carter

US Patent:

6654308, Nov 25, 2003

Filed:

Dec 23, 2002

Appl. No.:

10/326779

Inventors:

Richard J. Carter - Los Altos CA

Assignee:

Hewlett-Packard Development Company, LP. - Houston TX

International Classification:

G11C 800

US Classification:

36523005, 36518901

Abstract:

A control unit is described that allows multiple data memory units to be combined to construct a memory having a greater number of write ports than is selectable from a design library. A control unit is provided using control memory units to keep track of which of the data memory units contain the most recently written version of the data for each address of the constructed memory. The data memory units and control memory units do not require more write ports than the maximum number available for memory devices selectable from the design library.

US Patent:

6754130, Jun 22, 2004

Filed:

Dec 23, 2002

Appl. No.:

10/326405

Inventors:

Richard J. Carter - Los Altos CA

Assignee:

Hewlett-Packard Development Company, LP. - Houston TX

International Classification:

G11C 800

US Classification:

36523005, 36523002

Abstract:

Exemplary embodiments of the present invention are directed to providing a memory having N write ports, where N is greater than one. The memory includes a first data memory unit having a plurality of storage locations addressable by a range of addresses, and having less than N write ports. The memory also has a second data memory unit having a plurality of storage locations addressable by the range of addresses, the second data memory unit having less than N write ports. The memory includes a control unit configured to select among the first data memory unit and the second data memory unit in response to a read command having an associated read address which falls within the address range. The control unit includes multiple control memory units, each having less than N write ports. The control unit comprises at least one write-insert unit producing insert data for one of the control memory units, the at least one write-insert unit receiving read data from at least one other control memory unit.

US Patent:

6785872, Aug 31, 2004

Filed:

Jan 22, 2002

Appl. No.:

10/051078

Inventors:

Richard J. Carter - Los Altos CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

716 3, 716 19

Abstract:

A system and method is provided for creating a digital circuit, such as a configured FPGA or a VLSI chip. User code includes algorithm specifications having precisely defined operators and variables, data representation specifications and data communication specifications. The user code is compiled to create a digital circuit. For example, the compiled user code is used to generate either a hard-wired digital circuit or the configuration instructions for configuring a re-configurable digital circuit.

US Patent:

6813215, Nov 2, 2004

Filed:

Dec 23, 2002

Appl. No.:

10/326091

Inventors:

Richard J. Carter - Los Altos CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 700

US Classification:

36523005, 36518901

Abstract:

Exemplary embodiments of the present invention are directed to providing a memory having N write ports, where N is greater than one. The memory includes a first data memory unit having a plurality of storage locations addressable by a range of addresses and having less than N write ports; the memory also includes a second data memory unit having a plurality of storage locations addressable by the range of addresses, the second data memory having less than N write ports. The memory further includes a control unit configured to select among the first and second memory units in response to a read command having an associated read address which falls within the address range. The control unit includes multiple control memory units each with less than N write ports.

US Patent:

6968275, Nov 22, 2005

Filed:

Feb 22, 2002

Appl. No.:

10/080018

Inventors:

J Barry Shackleford - Sunnyvale CA, US
Gregory S. Snider - Mountain View CA, US
Richard J Carter - Menlo Park CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G01N033/48
G05B015/00

US Classification:

702 27, 700 1

Abstract:

The present invention provides a method and apparatus to significantly accelerate the searching process based on the Monte Carlo principle and the lattice model. Specifically, the energy status of a lattice-based protein conformation is evaluated by modeling the folding process through a pipelined digital circuit using a number of state machines. The pipelined digital circuit reduces the time required for the determination of the energy status of a particular conformation and, therefore, significantly accelerates the searching speed for the lowest energy status. The present invention also permits real-time tuning of problem parameters by the experimenter.

US Patent:

7082453, Jul 25, 2006

Filed:

Sep 27, 2002

Appl. No.:

10/255611

Inventors:

J. Barry Shackleford - Portola Valley CA, US
Richard J. Carter - Los Altos CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 7/50

US Classification:

708672

Abstract:

The present invention is a counter that takes advantage of the speed and implementation of the LFSR counter by utilizing separate digit counters, each digit counter having a period that is a relative prime to the other digit counter periods. The total period will be the product of all the digit counter periods. Since all digits count independently, there is no carry structure between the digits and hence no delay incurred by carry chains. The pseudorandom number counting sequence for each digit still occurs but is ameliorated by the fact that the digital periods are small and can readily be converted to decimal equivalents by table-lookup and residue lookup.

US Patent:

7376741, May 20, 2008

Filed:

Mar 19, 1999

Appl. No.:

09/272810

Inventors:

Richard J. Carter - Menlo Park CA, US
Ludmila Cherkasova - Sunnyvale CA, US

Assignee:

Hewlett-Packard Development Corporation, L.P. - Houston TX

International Classification:

G06F 15/16

US Classification:

709228, 709227, 709237

Abstract:

An HTTP server is programmed to detect timed-out client requests by inferring states of its client-server connections. These connections, being full-duplex, can each be viewed as including a client-to-server channel and a server-to-client channel. The state of the server-to-client channel can be inferred by examining local server information to determine whether the client-to-server channel is still established. The server processes a request by a client if the inferred state indicates that the server-to-client channel is still established, and the server terminates the client request if the inferred state indicates that the server-to-client channel is no longer established. Consequently, the server does not expend resources by processing timed-out or dead client requests.

US Patent:

7571200, Aug 4, 2009

Filed:

Apr 24, 2002

Appl. No.:

10/131630

Inventors:

J. Barry Shackleford - Portola Valley CA, US
Richard J. Carter - Los Altos CA, US
Motoo Tanaka - Pleasanton CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1/02

US Classification:

708250, 708251

Abstract:

A seedable pseudo-random number generator. A linear feedback shift register (LFSR) arrangement is used to generate a first pseudo-random number, and a cellular automata is used to generate a second pseudo-random number. The bits of the LFSR arrangement are XORed with bits of the cellular automata to generate the output pseudo-random number.