Richard M Chapman

US Patent:

6348719, Feb 19, 2002

Filed:

Aug 14, 1996

Appl. No.:

08/698251

Inventors:

Richard A. Chapman - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2976

US Classification:

257412, 257392

Abstract:

A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor comprises a polysilicon gate doped at first dopant level. Low voltage NMOS transistor comprises a polysilicon gate doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor comprises a polysilicon gate doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate doped at a fourth dopant level. The fourth dopant level is higher than the third.

US Patent:

6376293, Apr 23, 2002

Filed:

Mar 29, 2000

Appl. No.:

09/537271

Inventors:

Richard A. Chapman - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218238

US Classification:

438199, 438201, 438222, 438226, 438230, 257 69, 257204

Abstract:

A method of fabricating a CMOS transistor to construct shallow drain extenders ( ) using a replacement gate design. The method involves forming epitaxial layers ( ) and ( ) the will later function as shallow drain extensions. The etching of the replacement gate ( ) and the formation of inner sidewalls ( ) serve to define the transistor gate length.

US Patent:

55959229, Jan 21, 1997

Filed:

Oct 28, 1994

Appl. No.:

8/330655

Inventors:

Howard L. Tigelaar - Allen TX
Bert R. Riemenschneider - Plano TX
Richard A. Chapman - Dallas TX
Andrew T. Appel - Dallas TX

Assignee:

Texas Instruments - Dallas TX

International Classification:

H01L 21265
H01L 2170
H01L 2700

US Classification:

437 40

Abstract:

One embodiment of the present invention is a method of simultaneously forming high-voltage (12) and low-voltage (10) devices on a single substrate (14), the method comprising: forming a thin oxide layer (18) on the substrate, the thin oxide layer having a desired thickness for a gate oxide for the low-voltage device; selectively forming a gate structure (30) for the high-voltage device, the thin oxide is situated between the gate structure and the substrate; and selectively thickening the thin oxide under the gate structure while keeping the thin oxide layer utilized for the low-voltage device at the desired thickness.

US Patent:

43607322, Nov 23, 1982

Filed:

Jun 16, 1980

Appl. No.:

6/159990

Inventors:

Richard A. Chapman - Dallas TX
Adam J. Lewis - Richardson TX
Jaroslav Hynecek - Richardson TX
Michael A. Kinch - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01J 3149

US Classification:

250332

Abstract:

An infrared charge transfer device (CTD) imaging system is disclosed which includes an optic system for focusing infrared energy emanating from a scene, a detector matrix for receiving the focused infrared energy and converting it to electrical signals representative of the intensity of the infrared energy, and a video processor for processing the electrical signals into video signals. The detector matrix of the system is a plurality of IR detector cells arranged in rows and columns. Each detector cell includes a substrate of semiconductor material, an integrating electrode, a drain electrode, a transfer electrode and insulating layers. The integrating electrode is centrally disposed with respect to the drain and transfer electrodes with the integrating electrode in a spaced relationship with the drain electrode. The integrating and drain electrodes form first level MIS electrodes on the semiconductor substrate. The transfer gate forms a second level MIS electrode as to the semiconductor substrate and overlaps the space between the integrating and drain electrodes.

US Patent:

51983788, Mar 30, 1993

Filed:

Dec 10, 1990

Appl. No.:

7/609969

Inventors:

Mark S. Rodder - Dallas TX
Richard A. Chapman - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265

US Classification:

437 41

Abstract:

An elevated transistor is provided having minimized junctions (33) and a polysilicon pad (27) over the transistor insulating regions (12) and partially over the moat (14). A conductive layer (32) overlays the polysilicon pad (27) and partially overlays the moat (14) in the interim areas (29).

US Patent:

44293305, Jan 31, 1984

Filed:

Apr 18, 1980

Appl. No.:

6/141498

Inventors:

Richard A. Chapman - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 533
H04N 315

US Classification:

358113

Abstract:

An infrared random access imager system is disclosed which includes a scanning mechanism, a random access imager detector matrix, and a video signal processor. The scanning mechanism scans the infrared energy emanating from a scene in the field-of-view. The random access imager detector matrix stores charges as charge packets representative of the infrared energy impinging thereon and the video signal processor processes the charge packets into video signals. Each random access imager detector matrix element comprises a modified charge injection device, which has two electrodes per unit cell, and horizontal and vertical metal-lead address lines, to which is added a third electrode. The third electrode is a transfer gate which transfers the charge of the detector element into a read line and keeps the charge from one detector from spilling into the detector well of an adjoining unit cell. Thus, charge carriers are created by photoabsorption and collected in the detector well (storage well).

US Patent:

49623222, Oct 9, 1990

Filed:

Oct 25, 1989

Appl. No.:

7/426520

Inventors:

Richard A. Chapman - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 3353
H01L 2978
H01L 2702
G11C 1140

US Classification:

307304

Abstract:

The disclosure relates to a MOSFET-protected nonvolatile capacitor cell which has a storage gate and a nonvolatile stack thereunder, the cell having a heavily doped n+ ring surrounding the storage gate and an n-type tank disposed beneath the stack and electrically connected to the n+ type ring.

US Patent:

50100327, Apr 23, 1991

Filed:

Oct 5, 1989

Appl. No.:

7/417386

Inventors:

Thomas E. Tang - Dallas TX
Che-Chia Wei - Plano TX
Roger A. Haken - Richardson TX
Richard A. Chapman - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21336

US Classification:

437 57

Abstract:

A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.