Richard Conti

US Patent:

6335261, Jan 1, 2002

Filed:

May 31, 2000

Appl. No.:

09/584355

Inventors:

Wesley Natzle - New Paltz NY
Richard A. Conti - Mount Kisco NY
Laertis Economikos - Wappingers Falls NY
Thomas Ivers - Hopewell Jct. NY
George D. Papasouliotis - Fishkill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438435, 438221, 438424, 438685, 438694, 438696, 438758, 438762, 438765, 438775, 438788

Abstract:

A method is described for filling a high-aspect-ratio feature, in which compatible deposition and etching steps are performed in a sequence. The feature is formed as an opening in a substrate having a surface; a fill material is deposited at the bottom of the feature and on the surface of the substrate; deposition on the surface adjacent the feature causes formation of an overhang structure partially blocking the opening. The fill material is then reacted with a reactant to form a solid reaction product having a greater specific volume than the fill material. The overhang structure is thus converted into a reaction product structure blocking the opening. The reaction product (including the reaction product structure) is then desorbed, thereby exposing unreacted fill material at the bottom of the feature. The depositing and reacting steps may be repeated, with a final depositing step to fill the feature. Each sequence of depositing, reacting and desorbing reduces the aspect ratio of the feature.

US Patent:

7326651, Feb 5, 2008

Filed:

Dec 14, 2004

Appl. No.:

10/905068

Inventors:

Heidi Baks - Poughkeepsie NY, US
Richard A. Bruff - Wappingers Falls NY, US
Richard A. Conti - Katonah NY, US
Allan Upham - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/302

US Classification:

438706, 438704, 438717, 438725, 438736, 438694, 438696

Abstract:

This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized.

US Patent:

7955926, Jun 7, 2011

Filed:

Mar 26, 2008

Appl. No.:

12/055682

Inventors:

Wesley C. Natzle - New Paltz NY, US
Renee T. Mo - Briarcliff Manor NY, US
Rashmi Jha - Wappingers Falls NY, US
Kathryn T. Schonenberg - Wappingers Falls NY, US
Richard A. Conti - Katonah NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438240, 438197, 257310, 257544

Abstract:

In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

US Patent:

20110241085, Oct 6, 2011

Filed:

Mar 31, 2010

Appl. No.:

12/751891

Inventors:

David L. O'Meara - Poughkeepsie NY, US
Anthony Dip - Cedar Creek TX, US
Aelan Mosden - Poughkeepsie NY, US
Pao-Hwa Chou - Kofu-city, JP
Richard A. Conti - Katonah NY, US

Assignee:

TOKYO ELECTRON LIMITED - Tokyo
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78
H01L 21/311

US Classification:

257288, 438696, 257E21249, 257E29255

Abstract:

A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.

US Patent:

20110241128, Oct 6, 2011

Filed:

Mar 31, 2010

Appl. No.:

12/751926

Inventors:

David L. O'Meara - Poughkeepsie NY, US
Anthony Dip - Cedar Creek TX, US
Aelan Mosden - Poughkeepsie NY, US
Pao-Hwa Chou - Kofu-city, JP
Richard A. Conti - Katonah NY, US

Assignee:

TOKYO ELECTRON LIMITED - Tokyo
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257408, 438299, 257E21409, 257E29255

Abstract:

A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.

US Patent:

52680690, Dec 7, 1993

Filed:

Jun 8, 1992

Appl. No.:

7/895493

Inventors:

Jonathan D. Chapple-Sokol - Poughkeepsie NY
Richard A. Conti - Mount Kisco NY
David E. Kotecki - Hopewell Junction NY
Andrew H. Simon - Fishkill NY
Manu Tejwani - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

156646

Abstract:

Anhydrous ammonium fluoride is used as a safe source of hydrogen fluoride for etching native or other silicon dioxide layers from silicon substrates. Heating the anhydrous ammonium fluoride above its sublimation temperature results in the generation of hydrogen fluoride gas which etches the silicon dioxide. Controlled amounts of water vapor are used during the etch reaction to ensure complete etching of the thin oxide layers down to within hundredths of a monolayer and to achieve precise etch rate control.