Richard H Conti

US Patent:

D471053, Mar 4, 2003

Filed:

Feb 26, 2002

Appl. No.:

29/156180

Inventors:

Richard J Conti - Eagle Lake FL 33839

International Classification:

0701

US Classification:

D 7301, D7398

US Patent:

20210151579, May 20, 2021

Filed:

Dec 29, 2020

Appl. No.:

17/136169

Inventors:

- Armonk NY, US
Richard A. Conti - Altamont NY, US
Eric Miller - Watervliet NY, US
Son Nguyen - Schenectady NY, US

International Classification:

H01L 29/66
H01L 21/02
H01L 29/417

Abstract:

A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

US Patent:

20210111077, Apr 15, 2021

Filed:

Dec 22, 2020

Appl. No.:

17/130214

Inventors:

- Armonk NY, US
Richard A. Conti - Altamont NY, US
ChoongHyun Lee - Rensselaer NY, US

International Classification:

H01L 21/8234
H01L 29/78
H01L 29/06
H01L 29/66
H01L 27/088
H01L 29/165
H01L 21/308
H01L 21/02

Abstract:

A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.

US Patent:

20200312909, Oct 1, 2020

Filed:

Mar 27, 2019

Appl. No.:

16/366309

Inventors:

- ARMONK NY, US
Richard A. Conti - Altamont NY, US
RUILONG XIE - NISKAYUNA NY, US
Kangguo Cheng - Schenectady NY, US

International Classification:

H01L 27/24
H01L 29/45
H01L 21/285
H01L 29/66
H01L 45/00

Abstract:

A middle-of-line (MOL) structure is provided and includes device and resistive memory (RM) regions. The device region includes trench silicide (TS) metallization, a first interlayer dielectric (ILD) portion and a first dielectric cap portion disposed over the TS metallization and the first ILD portion. The RM region includes a second dielectric cap portion, a second ILD portion and an RM resistor interposed between the second dielectric cap portion and the second ILD portion.

US Patent:

20200273753, Aug 27, 2020

Filed:

Feb 25, 2019

Appl. No.:

16/284682

Inventors:

- Armonk NY, US
Richard A. Conti - Altamont NY, US
ChoongHyun Lee - Rensselaer NY, US

International Classification:

H01L 21/8234
H01L 29/78
H01L 29/06
H01L 29/66
H01L 27/088
H01L 21/308
H01L 21/02
H01L 29/165

Abstract:

A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.

US Patent:

20200266111, Aug 20, 2020

Filed:

Apr 21, 2020

Appl. No.:

16/854850

Inventors:

- Armonk NY, US
Kangguo Cheng - Schenectady NY, US
Michael P. Belyansky - Halfmoon NY, US
Oleg Gluschenkov - Tannersville NY, US
Richard A. Conti - Altamont NY, US
James Kelly - Schenectady NY, US
Balasubramanian Pranatharthiharan - Watervliet NY, US

International Classification:

H01L 21/8238
H01L 27/12
H01L 23/60
H01L 21/765
H01L 21/84
H01L 27/092

Abstract:

Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

US Patent:

20200126805, Apr 23, 2020

Filed:

Oct 19, 2018

Appl. No.:

16/165786

Inventors:

- Armonk NY, US
Muthumanickam Sankarapandian - Niskayuna NY, US
Richard A. Conti - Altamont NY, US
Michael P. Belyansky - Halfmoon NY, US

International Classification:

H01L 21/311
H01L 21/762
H01L 29/66
H01L 29/78

Abstract:

Highly selective dry etching techniques for VFET STI recess are provided. In one aspect, a method for dry etching includes: contacting a wafer including an oxide with at least one etch gas under conditions sufficient to etch the oxide at a rate of less than about 30 Å/min; removing a byproduct of the etch from the wafer using a thermal treatment; and repeating the contacting step followed by the removing step multiple times until a desired recess of the oxide has been achieved. A method of forming a VFET device is also provided.

US Patent:

20200126867, Apr 23, 2020

Filed:

Oct 17, 2018

Appl. No.:

16/163275

Inventors:

- Armonk NY, US
Kangguo Cheng - Schenectady NY, US
Michael P. Belyansky - Halfmoon NY, US
Oleg Gluschenkov - Tannersville NY, US
Richard A. Conti - Altamont NY, US
James Kelly - Schenectady NY, US
Balasubramanian Pranatharthiharan - Watervliet NY, US

International Classification:

H01L 21/8238
H01L 27/092
H01L 21/84
H01L 27/12
H01L 21/765
H01L 23/60

Abstract:

Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.