Richard Lyle Elliott

US Patent:

6593657, Jul 15, 2003

Filed:

Mar 3, 1997

Appl. No.:

08/811124

Inventors:

Richard L. Elliott - Meridian ID
Guy F. Hudson - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2348

US Classification:

257765, 257767, 257764

Abstract:

A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate. Article qualities are achieved by the inventive method, including reduced interfacial resistance and its consequent faster signal speed for the structure, reduced metal creep where additional selected alloys are allowed to diffuse a selected quantity of preferred alloying elements from the first metal layer to the second metal layer, improved depth-of-focus requirements for patterning metallization lines, and resistance of electromigration in aluminum metallization lines.

US Patent:

6713384, Mar 30, 2004

Filed:

Jan 16, 1998

Appl. No.:

09/007949

Inventors:

Richard L. Elliott - Meridian ID
Guy F. Hudson - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 214763

US Classification:

438625, 438627, 438660, 438688

Abstract:

A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate. Article qualities are achieved by the inventive method, including reduced interfacial resistance and its consequent faster signal speed for the structure, reduced metal creep where additional selected alloys are allowed to diffuse a selected quantity of preferred alloying elements from the first metal layer to the second metal layer, improved depth-of-focus requirements for patterning metallization lines, and resistance of electromigration in aluminum metallization lines.

US Patent:

7294570, Nov 13, 2007

Filed:

Mar 29, 2004

Appl. No.:

10/812117

Inventors:

Richard L. Elliott - Meridian ID, US
Guy F. Hudson - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/44

US Classification:

438653, 438655, 438660, 438664, 257751, 257752, 257757, 257765, 257E21577, 257E21584, 257E21585

Abstract:

A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate. Article qualities are achieved by the inventive method, including reduced interfacial resistance and its consequent faster signal speed for the structure, reduced metal creep where additional selected alloys are allowed to diffuse a selected quantity of preferred alloying elements from the first metal layer to the second metal layer, improved depth-of-focus requirements for patterning metallization lines, and resistance of electromigration in aluminum metallization lines.

US Patent:

55408109, Jul 30, 1996

Filed:

Jun 20, 1995

Appl. No.:

8/493205

Inventors:

Gurtej Sandhu - Boise ID
Richard L. Elliott - Boise ID
Trung T. Doan - Boise ID
Jody D. Larsen - Boise ID

Assignee:

Micron Technology Inc. - Boise ID

International Classification:

H01L 2100
B24B 100

US Classification:

1566361

Abstract:

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the cmp process utilizes a system of closely regulating the timing of the two chemical process. Specifically, during a first time period, both chemicals are applied; thus increasing speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, thus slowing down the chemical action and importantly achieving a greater degree of planerization than is capable by the two chemical first time period.

US Patent:

59566124, Sep 21, 1999

Filed:

Aug 9, 1996

Appl. No.:

8/689535

Inventors:

Richard L. Elliott - Meridian ID
John H. Givens - Meridian ID
Guy F. Hudson - Boise ID

Assignee:

MICRON Technology, Inc. - Boise ID

International Classification:

H01L 21441

US Classification:

438637

Abstract:

A contact space filled with conductive material having good step coverage is disclosed. The contact space is formed in a dielectric layer with an upper surface. The contact space has sidewalls comprised of the dielectric layer and a bottom comprised of an underlying layer. The contact space is filled by first depositing a layer of an amorphous material such as TiAl. sub. 3 over the bottom and sidewalls of the contact space, then filling the contact space with a metallic fill material such as an aluminum-containing fill material. The amorphous material is chosen particularly to have low reactivity with the metallic fill material, so that mobility of the metallic fill material over the surface upon which it is deposited is facilitated.

US Patent:

59942240, Nov 30, 1999

Filed:

Dec 17, 1997

Appl. No.:

8/992399

Inventors:

Gurtej S. Sandhu - Boise ID
Richard L. Elliott - Boise ID
Trung T. Doan - Boise ID
Jody D. Larsen - Boise ID

Assignee:

Micron Technology Inc. - Boise ID

International Classification:

H01L 21304

US Classification:

438692

Abstract:

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the cmp process utilizes a system of closely regulating the timing of the two chemical process. Specifically, during a first time period, both chemicals are applied; thus increasing speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, thus slowing down the chemical action and importantly achieving a greater degree of planerization than is capable by the two chemical first time period.

US Patent:

56905408, Nov 25, 1997

Filed:

Feb 23, 1996

Appl. No.:

8/606418

Inventors:

Richard L. Elliott - Meridian ID
Michael A. Walker - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B24B 722

US Classification:

451 41

Abstract:

The present invention is a polishing pad for use in chemical-mechanical planarization of semiconductor wafers by placing a wafer against a polishing surface of the polishing pad while rotating the polishing pad about its center in the presence of a polishing slurry. The polishing surface has formed therein one or more grooves extending in a spiral inwardly from the periphery to the center of the polishing pad. As a result, slurry is transported inwardly toward the center or toward the periphery of the polishing pad depending upon the circumferential direction of the spiral relative to the direction of rotation of the polishing pad.

US Patent:

59851031, Nov 16, 1999

Filed:

Aug 14, 1997

Appl. No.:

8/911151

Inventors:

John H. Givens - Boise ID
Richard L. Elliott - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

C23C 1434

US Classification:

20419212

Abstract:

A method is disclosed for improved side wall and bottom coverage of high aspect ratio space situated upon a substrate in two (2) steps. A lining is formed on a side wall surface of the space that terminated at a bottom surface. An opening then remains to a void defined by the lining and the bottom surface. The void is filled with a material passing through the opening to the space. When sputtered, the lining can be formed by a less-collimated sputtered particle flux, and the void can be filled by a collimated sputtered particle flux. The lining can be formed by flux in a plasma formed from a first gas having a neutral to ion ratio, and the void can be filled by a flux in a plasma formed from a second gas having a neutral to ion ratio lower than that of the first. Also, the lining can be formed by a flux in a plasma formed from a first gas having an atomic mass, and the void can be filled by a flux in a plasma formed from a second gas having an atomic mass lower than that of the first. The lining can be formed by sputtering a target having a crystal structure not preferentially oriented to maximize collimation thereof, and the void can be filled with a flux from a target having a crystal structure preferentially oriented to maximize collimation thereof.