Richard Carr Elliott

US Patent:

6593657, Jul 15, 2003

Filed:

Mar 3, 1997

Appl. No.:

08/811124

Inventors:

Richard L. Elliott - Meridian ID
Guy F. Hudson - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2348

US Classification:

257765, 257767, 257764

Abstract:

A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate. Article qualities are achieved by the inventive method, including reduced interfacial resistance and its consequent faster signal speed for the structure, reduced metal creep where additional selected alloys are allowed to diffuse a selected quantity of preferred alloying elements from the first metal layer to the second metal layer, improved depth-of-focus requirements for patterning metallization lines, and resistance of electromigration in aluminum metallization lines.

US Patent:

6713384, Mar 30, 2004

Filed:

Jan 16, 1998

Appl. No.:

09/007949

Inventors:

Richard L. Elliott - Meridian ID
Guy F. Hudson - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 214763

US Classification:

438625, 438627, 438660, 438688

Abstract:

A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate. Article qualities are achieved by the inventive method, including reduced interfacial resistance and its consequent faster signal speed for the structure, reduced metal creep where additional selected alloys are allowed to diffuse a selected quantity of preferred alloying elements from the first metal layer to the second metal layer, improved depth-of-focus requirements for patterning metallization lines, and resistance of electromigration in aluminum metallization lines.

US Patent:

7294570, Nov 13, 2007

Filed:

Mar 29, 2004

Appl. No.:

10/812117

Inventors:

Richard L. Elliott - Meridian ID, US
Guy F. Hudson - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/44

US Classification:

438653, 438655, 438660, 438664, 257751, 257752, 257757, 257765, 257E21577, 257E21584, 257E21585

Abstract:

A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate. Article qualities are achieved by the inventive method, including reduced interfacial resistance and its consequent faster signal speed for the structure, reduced metal creep where additional selected alloys are allowed to diffuse a selected quantity of preferred alloying elements from the first metal layer to the second metal layer, improved depth-of-focus requirements for patterning metallization lines, and resistance of electromigration in aluminum metallization lines.

US Patent:

8318762, Nov 27, 2012

Filed:

May 18, 2009

Appl. No.:

12/934375

Inventors:

Jeffrey W. Corbett - Niantic CT, US
Richard Elliott - Seattle WA, US
Kevin Freeman-Cook - Carlsbad CA, US
David A. Griffith - Old Saybrook CT, US
Dennis P. Phillion - St Charles MO, US

Assignee:

Pfizer Inc. - New York NY

International Classification:

C07D 491/107
A61K 31/436
A61K 31/438

US Classification:

514278, 546 20

Abstract:

The invention provides compounds of Formula (1) or a pharmaceutically acceptable salt of said compound, wherein R, R, and Rare as described herein; pharmaceutical compositions thereof; and the use thereof in treating diseases, conditions or disorders modulated by the inhibition of acetyl-CoA carboxylase enzyme(s) in an animal.

US Patent:

20090270435, Oct 29, 2009

Filed:

Nov 16, 2007

Appl. No.:

12/514596

Inventors:

Jeffrey Wayne Corbett - Niantic CT, US
Richard Louis Elliott - Seattle WA, US
Andrew Simon Bell - Kent, GB

International Classification:

A61K 31/438
C07D 491/107
A61P 3/04

US Classification:

514278, 546 17

Abstract:

The invention provides compounds of Formula (1) or a pharmaceutically acceptable salt of said compound, wherein R, R, R, R, R, R, R, Rand Rare as described herein; pharmaceutical compositions thereof; and the use thereof in treating mammals suffering from the condition of being overweight.

US Patent:

55408109, Jul 30, 1996

Filed:

Jun 20, 1995

Appl. No.:

8/493205

Inventors:

Gurtej Sandhu - Boise ID
Richard L. Elliott - Boise ID
Trung T. Doan - Boise ID
Jody D. Larsen - Boise ID

Assignee:

Micron Technology Inc. - Boise ID

International Classification:

H01L 2100
B24B 100

US Classification:

1566361

Abstract:

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the cmp process utilizes a system of closely regulating the timing of the two chemical process. Specifically, during a first time period, both chemicals are applied; thus increasing speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, thus slowing down the chemical action and importantly achieving a greater degree of planerization than is capable by the two chemical first time period.

US Patent:

59566124, Sep 21, 1999

Filed:

Aug 9, 1996

Appl. No.:

8/689535

Inventors:

Richard L. Elliott - Meridian ID
John H. Givens - Meridian ID
Guy F. Hudson - Boise ID

Assignee:

MICRON Technology, Inc. - Boise ID

International Classification:

H01L 21441

US Classification:

438637

Abstract:

A contact space filled with conductive material having good step coverage is disclosed. The contact space is formed in a dielectric layer with an upper surface. The contact space has sidewalls comprised of the dielectric layer and a bottom comprised of an underlying layer. The contact space is filled by first depositing a layer of an amorphous material such as TiAl. sub. 3 over the bottom and sidewalls of the contact space, then filling the contact space with a metallic fill material such as an aluminum-containing fill material. The amorphous material is chosen particularly to have low reactivity with the metallic fill material, so that mobility of the metallic fill material over the surface upon which it is deposited is facilitated.

US Patent:

59942240, Nov 30, 1999

Filed:

Dec 17, 1997

Appl. No.:

8/992399

Inventors:

Gurtej S. Sandhu - Boise ID
Richard L. Elliott - Boise ID
Trung T. Doan - Boise ID
Jody D. Larsen - Boise ID

Assignee:

Micron Technology Inc. - Boise ID

International Classification:

H01L 21304

US Classification:

438692

Abstract:

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the cmp process utilizes a system of closely regulating the timing of the two chemical process. Specifically, during a first time period, both chemicals are applied; thus increasing speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, thus slowing down the chemical action and importantly achieving a greater degree of planerization than is capable by the two chemical first time period.