A system and method is disclosed for providing a variable breakdown bipolar transistor. A trench is etched in a substrate between a first area (base/emitter area) and a second area (sinker/collector area). The sinker/collector contact area and a portion of the bottom of the trench adjacent to the sinker/collector area are then heavily doped. The lateral distance between the base/emitter area and the edge of the heavily doped trench determines the breakdown voltage between the emitter and collector and between the base and collector. Heat treatment diffuses the dopant in the bottom of the trench laterally and diffuses the dopant in the sinker/collector area downward until the two areas are joined to form a unified sinker/collector structure.
System And Method For Providing A Self Heating Adjustable Tisiresistor
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/20
US Classification:
438384, 438382, 257E21006
Abstract:
A system and method is disclosed for providing a self heating adjustable titanium disilicon (TiSi) resistor. A triangularly shaped layer of polysilicon is placed a layer of insulation material. A layer of titanium is applied over the polysilicon and heated to form a layer of C49 type of TiSi. A current is then applied to the small end of the triangularly shaped layer of C49 TiSi. The current generates heat in a high resistance portion of the triangularly shaped layer of C49 TiSiand converts a portion of the C49 TiSito C54 TiSi. The lower resistance of the C54 TiSidecreases the effective resistance of the resistor. A desired value of resistance may be selected by adjusting the magnitude of the applied current.
System And Method For Providing Improved Trench Isolation Of Semiconductor Devices
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/762
US Classification:
438430, 257E21546
Abstract:
A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. Then a silicon liner is grown in the trench. The trench is then filled with polysilicon material. Polysilicon material is also deposited on top of the filled trench to protect the silicon dioxide liner from the effects of subsequent etch procedures and oxidation procedures. The initial height of the polysilicon material is selected to be large enough to allow the polysilicon material to survive the subsequent etch procedures and oxidation procedures.
System And Method For Providing A Self Heating Adjustable Tisiresistor
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 29/00
US Classification:
257537, 257536
Abstract:
A system and method is disclosed for providing a self heating adjustable titanium disilicon (TiSi) resistor. A triangularly shaped layer of polysilicon is placed a layer of insulation material. A layer of titanium is applied over the polysilicon and heated to form a layer of C49 type of TiSi. A current is then applied to the small end of the triangularly shaped layer of C49 TiSi. The current generates heat in a high resistance portion of the triangularly shaped layer of C49 TiSiand converts a portion of the C49 TiSito C54 TiSi. The lower resistance of the C54 TiSidecreases the effective resistance of the resistor. A desired value of resistance may be selected by adjusting the magnitude of the applied current.
Method For Providing A Deep Connection To Substrate Or Buried Layer In A Semiconductor Device
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 29/76 H01L 29/94 H01L 31/00
US Classification:
257374, 257510, 257E21545, 257E21546
Abstract:
A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial silicon layer at the bottom of the central shallow trench. First and third doped layers are created in the epitaxial silicon layer adjacent to the central shallow trench. An oxide layer is then deposited to fill the three trenches. The second doped layer is diffused vertically down to the substrate. The first and third doped layers are diffused vertically down to the second doped layer. Lateral diffusion of the first and third doped layers is constrained by the oxide layer in the three trenches.
System And Method For Providing A Deep Connection To A Substrate Or Buried Layer Of A Semiconductor Device
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/425
US Classification:
438514, 438542, 257E21545, 257E21546
Abstract:
A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial silicon layer at the bottom of the central shallow trench. First and third doped layers are created in the epitaxial silicon layer adjacent to the central shallow trench. An oxide layer is then deposited to fill the three trenches. The second doped layer is diffused vertically down to the substrate. The first and third doped layers are diffused vertically down to the second doped layer. Lateral diffusion of the first and third doped layers is constrained by the oxide layer in the three trenches.
System And Method For Providing Improved Trench Isolation Of Semiconductor Devices
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 29/93
US Classification:
257500, 438296, 438404, 257E21545, 257E21551
Abstract:
A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. Then a silicon liner is grown in the trench. The trench is then filled with polysilicon material. Polysilicon material is also deposited on top of the filled trench to protect the silicon dioxide liner from the effects of subsequent etch procedures and oxidation procedures. The initial height of the polysilicon material is selected to be large enough to allow the polysilicon material to survive the subsequent etch procedures and oxidation procedures.
Semiconductor Apparatus Comprising Bipolar Transistors And Metal Oxide Semiconductor Transistors
Richard W. Foote - Kennedale TX, US Robert Oliver - Louisville CO, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 29/96
US Classification:
257370, 257E29293, 438202
Abstract:
A method for manufacturing a semiconductor apparatus is disclosed. The apparatus comprises double poly bipolar transistors and double poly metal oxide semiconductor (MOS) transistors. The bipolar transistors and the MOS transistors are manufactured in a unified process in which a first polysilicon layer (Poly1) is doped to form the extrinsic bases in the bipolar transistors and to form the gates in the MOS transistors. A second polysilicon layer (Poly2) is doped to form emitters in the bipolar transistors and to form the sources and drains in the MOS transistors. The method of the invention minimizes the number of manufacturing process steps.
Greenwood Elementary School Greenwood MO 1966-1969, John Adams Middle School Alexandria VA 1967-1971, Lees Summit Junior High School Lee's Summit MO 1969-1972