Richard W Foote

age ~96

from Belleview, FL

Also known as:
  • Richard William Foote
  • Richard Brett Foote
  • Brett Foote

Richard Foote Phones & Addresses

  • Belleview, FL
  • Ocala, FL
  • Hurricane, UT
  • 3120 Spring Grove Dr, Bedford, TX 76021 • 6823254187
  • Hot Springs National Park, AR
  • Cleveland, TX
  • Santa Clara, UT

Isbn (Books And Publications)

Abstract Algebra

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Author
Richard M. Foote

ISBN #
0130047716

Abstract Algebra

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Author
Richard M. Foote

ISBN #
0135693020

Abstract Algebra

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Author
Richard M. Foote

ISBN #
0471433349

Handbook of the Fruit Flies

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Author
Richard H. Foote

ISBN #
0801426235

Resumes

Richard Foote Photo 1

Do What You Love And You'll Never Work A Day In Your Life

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Position:
Co-Founder at Oregon Crepe Company
Location:
Salem, Oregon
Industry:
Food & Beverages
Work:
Oregon Crepe Company since Jan 2011
Co-Founder
Interests:
Food, Local Foods, natural foods, fresh local food, did I mention Food?
Certifications:
ServSafe Food Protection Manager Certification, ServeSafe.org
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Richard Foote

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Richard Foote Photo 3

Richard Foote

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Richard Foote Photo 4

Richard Foote

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Location:
United States
Name / Title
Company / Classification
Phones & Addresses
Richard L Foote
COMPASS PERFORMANCE IMPROVEMENT, LLC
Richard Foote
Incorporator/Organizer
YARD ART LLC
Nonclassifiable Establishments
230 Hereford Cir, Hot Springs, AR 71909

Us Patents

  • System And Method For Providing A Variable Breakdown Bipolar Transistor

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  • US Patent:
    7053464, May 30, 2006
  • Filed:
    Mar 16, 2004
  • Appl. No.:
    10/801739
  • Inventors:
    Richard W. Foote - Kennedale TX, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 27/082
  • US Classification:
    257565, 437 31, 437 33, 437 26, 437 27, 437 59, 437 76
  • Abstract:
    A system and method is disclosed for providing a variable breakdown bipolar transistor. A trench is etched in a substrate between a first area (base/emitter area) and a second area (sinker/collector area). The sinker/collector contact area and a portion of the bottom of the trench adjacent to the sinker/collector area are then heavily doped. The lateral distance between the base/emitter area and the edge of the heavily doped trench determines the breakdown voltage between the emitter and collector and between the base and collector. Heat treatment diffuses the dopant in the bottom of the trench laterally and diffuses the dopant in the sinker/collector area downward until the two areas are joined to form a unified sinker/collector structure.
  • System And Method For Providing A Self Heating Adjustable Tisiresistor

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  • US Patent:
    7166518, Jan 23, 2007
  • Filed:
    Mar 16, 2004
  • Appl. No.:
    10/801268
  • Inventors:
    Richard W. Foote - Kennedale TX, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 21/20
  • US Classification:
    438384, 438382, 257E21006
  • Abstract:
    A system and method is disclosed for providing a self heating adjustable titanium disilicon (TiSi) resistor. A triangularly shaped layer of polysilicon is placed a layer of insulation material. A layer of titanium is applied over the polysilicon and heated to form a layer of C49 type of TiSi. A current is then applied to the small end of the triangularly shaped layer of C49 TiSi. The current generates heat in a high resistance portion of the triangularly shaped layer of C49 TiSiand converts a portion of the C49 TiSito C54 TiSi. The lower resistance of the C54 TiSidecreases the effective resistance of the resistor. A desired value of resistance may be selected by adjusting the magnitude of the applied current.
  • System And Method For Providing Improved Trench Isolation Of Semiconductor Devices

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  • US Patent:
    7291541, Nov 6, 2007
  • Filed:
    Mar 18, 2004
  • Appl. No.:
    10/803273
  • Inventors:
    Richard W. Foote - Kennedale TX, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 21/762
  • US Classification:
    438430, 257E21546
  • Abstract:
    A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. Then a silicon liner is grown in the trench. The trench is then filled with polysilicon material. Polysilicon material is also deposited on top of the filled trench to protect the silicon dioxide liner from the effects of subsequent etch procedures and oxidation procedures. The initial height of the polysilicon material is selected to be large enough to allow the polysilicon material to survive the subsequent etch procedures and oxidation procedures.
  • System And Method For Providing A Self Heating Adjustable Tisiresistor

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  • US Patent:
    7332794, Feb 19, 2008
  • Filed:
    Dec 14, 2006
  • Appl. No.:
    11/639019
  • Inventors:
    Richard W. Foote - Kennedale TX, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 29/00
  • US Classification:
    257537, 257536
  • Abstract:
    A system and method is disclosed for providing a self heating adjustable titanium disilicon (TiSi) resistor. A triangularly shaped layer of polysilicon is placed a layer of insulation material. A layer of titanium is applied over the polysilicon and heated to form a layer of C49 type of TiSi. A current is then applied to the small end of the triangularly shaped layer of C49 TiSi. The current generates heat in a high resistance portion of the triangularly shaped layer of C49 TiSiand converts a portion of the C49 TiSito C54 TiSi. The lower resistance of the C54 TiSidecreases the effective resistance of the resistor. A desired value of resistance may be selected by adjusting the magnitude of the applied current.
  • Method For Providing A Deep Connection To Substrate Or Buried Layer In A Semiconductor Device

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  • US Patent:
    7348639, Mar 25, 2008
  • Filed:
    May 7, 2007
  • Appl. No.:
    11/800721
  • Inventors:
    Richard W. Foote - Kennedale TX, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 29/76
    H01L 29/94
    H01L 31/00
  • US Classification:
    257374, 257510, 257E21545, 257E21546
  • Abstract:
    A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial silicon layer at the bottom of the central shallow trench. First and third doped layers are created in the epitaxial silicon layer adjacent to the central shallow trench. An oxide layer is then deposited to fill the three trenches. The second doped layer is diffused vertically down to the substrate. The first and third doped layers are diffused vertically down to the second doped layer. Lateral diffusion of the first and third doped layers is constrained by the oxide layer in the three trenches.
  • System And Method For Providing A Deep Connection To A Substrate Or Buried Layer Of A Semiconductor Device

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  • US Patent:
    7547618, Jun 16, 2009
  • Filed:
    Jul 26, 2007
  • Appl. No.:
    11/881228
  • Inventors:
    Richard W. Foote - Kennedale TX, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 21/425
  • US Classification:
    438514, 438542, 257E21545, 257E21546
  • Abstract:
    A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial silicon layer at the bottom of the central shallow trench. First and third doped layers are created in the epitaxial silicon layer adjacent to the central shallow trench. An oxide layer is then deposited to fill the three trenches. The second doped layer is diffused vertically down to the substrate. The first and third doped layers are diffused vertically down to the second doped layer. Lateral diffusion of the first and third doped layers is constrained by the oxide layer in the three trenches.
  • System And Method For Providing Improved Trench Isolation Of Semiconductor Devices

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  • US Patent:
    7745902, Jun 29, 2010
  • Filed:
    Sep 21, 2007
  • Appl. No.:
    11/903349
  • Inventors:
    Richard W. Foote - Kennedale TX, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 29/93
  • US Classification:
    257500, 438296, 438404, 257E21545, 257E21551
  • Abstract:
    A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. Then a silicon liner is grown in the trench. The trench is then filled with polysilicon material. Polysilicon material is also deposited on top of the filled trench to protect the silicon dioxide liner from the effects of subsequent etch procedures and oxidation procedures. The initial height of the polysilicon material is selected to be large enough to allow the polysilicon material to survive the subsequent etch procedures and oxidation procedures.
  • Semiconductor Apparatus Comprising Bipolar Transistors And Metal Oxide Semiconductor Transistors

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  • US Patent:
    7772653, Aug 10, 2010
  • Filed:
    Feb 11, 2004
  • Appl. No.:
    10/777012
  • Inventors:
    Richard W. Foote - Kennedale TX, US
    Robert Oliver - Louisville CO, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 29/96
  • US Classification:
    257370, 257E29293, 438202
  • Abstract:
    A method for manufacturing a semiconductor apparatus is disclosed. The apparatus comprises double poly bipolar transistors and double poly metal oxide semiconductor (MOS) transistors. The bipolar transistors and the MOS transistors are manufactured in a unified process in which a first polysilicon layer (Poly1) is doped to form the extrinsic bases in the bipolar transistors and to form the gates in the MOS transistors. A second polysilicon layer (Poly2) is doped to form emitters in the bipolar transistors and to form the sources and drains in the MOS transistors. The method of the invention minimizes the number of manufacturing process steps.

License Records

Richard D Foote

License #:
RS125030A - Expired
Category:
Real Estate Commission
Type:
Real Estate Salesperson-Standard

Googleplus

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Richard Foote

Tagline:
Well then what?
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Richard Foote

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Richard Foote

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Richard Foote

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Richard Foote

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Richard Foote

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Richard Foote

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Richard Foote

Plaxo

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Richard Foote

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New York, NY

Classmates

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Richard Foote

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Schools:
All Saints Academy Breese IL 2001-2005
Community:
Juliann Brooks, Sandra Jansen
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Richard Foote

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Schools:
Atlanta High School Atlanta KS 1944-1948
Community:
Anton Brukman, Rufus Gatton, Jerry Foote, Eunice Whiteman, Wayne Thompson, Keith Dudeck
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Richard Foote

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Schools:
Shidler Elementary School Oklahoma City OK 1961-1965
Community:
Mandell Matheson, Shirley Coffman, Kenneth Slentz, Yvonne Spitek, Rosa Conner
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Richard Foote

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Schools:
Yale High School Yale SD 1949-1953
Community:
Harold Foote, Deanna Boetel, Linda Larson, Carl Foote, Jimboo Bobo, Larry Weidner, Don Boetel, Norman Dudley, Al Lawrence, Glenn Hofer, George Bich
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Richard Foote

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Schools:
Greenwood Elementary School Greenwood MO 1966-1969, John Adams Middle School Alexandria VA 1967-1971, Lees Summit Junior High School Lee's Summit MO 1969-1972
Community:
Gregory Farnham, Tammy Travis
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Richard Foote, Wilton Hig...

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Richard Foote, East High ...

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Richard Foote Photo 21

Richard Foote, Osceola Hi...

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Facebook

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Richard Foote

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Richard Foote

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Richard Foote

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Richard Foote

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Richard Foote

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Richard Foote

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Richard Foote

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Richard Foote

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Youtube

Richard Foote - Optimizer Statistics The Key...

Richard Foote - Optimizer Statistics The Key To Efficient, Scalable Da...

  • Duration:
    1h 29m 41s

Civil War author, Shelby Foote - Stars in The...

Interview of the late Shelby Foote on his book Stars in Their Courses,...

  • Duration:
    57m 1s

Sousamaphone - Richard Foote, Tuba 8th April

Our final set of submissions!! Today we had entries from some new and ...

  • Duration:
    1m

search Richard Foote location

  • Duration:
    30m 26s

A Neon Jazz Interview with Trombonist Richard...

Welcome to a new edition of the Neon Jazz interview series with Trombo...

  • Duration:
    11m 6s

Talking Dev with Richard Foote @ AUSOUG Conne...

This was footage taken from the AUSOUG Connect 2018 event in MEL. We h...

  • Duration:
    3m 8s

Myspace

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Richard Foote

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Locality:
Chester, United Kingdom
Gender:
Male
Birthday:
1942
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Richard Foote

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Locality:
Portland, Oregon
Gender:
Male
Birthday:
1925
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Richard Foote

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Locality:
eatonville, Washington
Gender:
Male
Birthday:
1948
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Richard Foote

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Locality:
Milton Keynes/ NP, East
Gender:
Male
Birthday:
1940
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Richard Foote

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Locality:
Spring Creek, Nevada
Gender:
Male
Birthday:
1955
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Richard Foote

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Locality:
NEW TOWN, North Dakota
Gender:
Male
Birthday:
1935

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