Richard L Freeman

US Patent:

54468485, Aug 29, 1995

Filed:

Jun 25, 1993

Appl. No.:

8/082175

Inventors:

Gary C. Whitlock - Mission Viejo CA
Richard D. Freeman - Mission Viejo CA
Keith S. Saldanha - Trabuco Canyon CA

International Classification:

G06F 1120

US Classification:

395280

Abstract:

An entry level data processing system is expandable, with low overhead, by a factor of two to a partitionable upgraded data processing system. This entry level system includes: 1) one system bus, 2) a central processing module (CPM), an input/output module (IOM), and a system control module (SCM)--all of which have one system bus port coupled to the system bus, 3) a memory module coupled via a memory bus to the system control module, and 4) a system expansion interface through which the entry level system is expanded to the upgraded system. In one particular preferred embodiment, the system expansion interface consists of a) a first connector on the SCM for externally connecting to and communicating with the memory bus, b) a second connector on the SCM for externally connecting to and communicating with the system bus, and c) an extension of the system bus through a switch in the SCM and a third connector on the SCM for externally connecting to and communicating with the extended system bus. To expand the entry level system to the upgraded system, a duplicate copy of the entry level data processing system as recited in 1-4 above is added along with a respective three port bus expansion module (BEM) in each copy of the entry level data processing system. This BEM, in each particular entry level system, intercouples the first and second connectors on the SCM of that same system to the third connector on the SCM of the other entry level system.

US Patent:

56341083, May 27, 1997

Filed:

Jul 2, 1996

Appl. No.:

8/674408

Inventors:

Richard D. Freeman - Mission Viejo CA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1200
G06F 1300

US Classification:

395445

Abstract:

A microcode cache memory is provided on a processor chip for supplying frequently used microcode instruction words to a processor. A bank of multiple Tag-Status RAMs holds addresses of microcode words residing in a bank of Data RAMs. A state machine and a special Least Recently Used Random Access Memory (LRU RAM) operate to maintain the more frequently used words in the Data RAMs so that more hits occur to provide the requested word in one clock cycle. A 90 bit microcode word with 20 fields enables the processor to perform multiple functions simultaneously in parallel.

US Patent:

55748830, Nov 12, 1996

Filed:

Nov 30, 1993

Appl. No.:

8/159883

Inventors:

Richard D. Freeman - Mission Viejo CA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1200
G06F 1300

US Classification:

395446

Abstract:

A multi-cache memory system resides on-chip with a system interface to external memory. A general cache memory holds frequently used data and OPCODES for delivery to a processor in one clock cycle. A microcode cache holds frequently used microcode instruction words for delivery to the processor in one clock cycle. Both general and microcode cache memories operate to replace less frequently used OPCODES, data words, and microcode instruction words, with more frequently used words.