Richard W Gillett

US Patent:

54267412, Jun 20, 1995

Filed:

Jan 14, 1994

Appl. No.:

8/182531

Inventors:

H. Bruce Butts - Redmond WA
James N. Leahy - Boston MA
Richard B. Gillett - Westford MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1100

US Classification:

395325

Abstract:

A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmitted on the bus (15). If the packet represents an event designated by the user to be of interest, a counter associated with the type of packet that was captured and interpreted is incremented by one. More specifically, a field programmable gate array (FPGA), configured by the user, defines the type of events to be counted. When an event to be accounted occurs, the FPGA (33) produces a counter address that is based on the nature of the event, and causes an enable pulse to be generated. The address is applied to the active one of two event counter banks (39a, 39b) via an input crossbar switch (37a). The enable pulse enables the addressed event counter to be incremented by one.