Richard M Greene

US Patent:

40816990, Mar 28, 1978

Filed:

Sep 14, 1976

Appl. No.:

5/723207

Inventors:

Ernie R. Hirt - Harleysville PA
William Mensch - Norristown PA
Richard M. Greene - Audubon PA

Assignee:

MOS Technology, Inc. - Norristown PA

International Classification:

H03K 1760
H03K 1704
H03K 1712
H03K 3353

US Classification:

307270

Abstract:

A circuit for energizing a memory drive line depending on the state of a control signal and the states of two complementary clocks uses a depletion mode MOS coupling device rather than the conventional enhancement mode device used in such cases, and energizes the memory line with a higher voltage than possible in the prior art and at better rise and fall times.

US Patent:

59733632, Oct 26, 1999

Filed:

Mar 9, 1995

Appl. No.:

8/401521

Inventors:

David R. Staab - San Jose CA
Richard M. Greene - Vincentown NJ
Mark L. Burgener - San Diego CA
Ronald E. Reedy - San Diego CA

Assignee:

Peregrine Semiconductor Corp. - San Diego CA

International Classification:

H01L 2994

US Classification:

257347

Abstract:

An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.

US Patent:

45188793, May 21, 1985

Filed:

Aug 31, 1983

Appl. No.:

6/528096

Inventors:

Richard M. Greene - Ambler PA

Assignee:

Solid State Scientific, Inc. - Willow Grove PA

International Classification:

H03K 519
G11C 706
G01R 19165
H03F 318

US Classification:

307530

Abstract:

A stable sense rail amplifier for CMOS memories is provided allowing very small voltage swings at or very close to the power supply rail to be transformed into substantially rail-to-rail swings. The input of the amplifier is coupled to the output of memory cells which may be designed to have output swings of 200 millivolts or less. These output swings are shifted to approximately the center of the range between the supply voltage and ground. While the level shifting is performed a small amount of linear gain is added. Subsequently the shifted signal is applied to a linear high gain amplifier stage. The high gain amplifier has as its output a substantially rail-to-rail signal. The total delay from the input rail of the amplifier to the high gain inverting amplifier stage is limited to the transfer time of a single CMOS FET. The amplifier is self-biasing and self-referencing.