Richard Ryan Greene

US Patent:

6538583, Mar 25, 2003

Filed:

Mar 15, 2002

Appl. No.:

10/098997

Inventors:

Phil Hallmark - Austin TX
Richard Greene - Austin TX

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 700

US Classification:

341 51, 341 59

Abstract:

A system for encoding and decoding information of a codeblock from a memory buffer that includes a context modeler that receives from the memory buffer the codeblock and divides the codeblock into a plurality of codesegments or decodes a codeblock worth of information from received compressed data. The codesegments includes a plurality of bits. The context modeler processes each of the codesegments individually by determining whether any of the bits need special coding information or decoding. The context modeler outputs coded bits associated with the bits that are coded with the special coding information and context information associated with the coded bits or outputs a codeblock worth of information to the memory buffer. An arithmetic coder receives the context information and coded bits and compresses the coded bits or receives compressed data and decompresses the compressed data to produce context information and coded bits.

US Patent:

8611652, Dec 17, 2013

Filed:

Dec 16, 2010

Appl. No.:

12/970653

Inventors:

James H. Jannard - Las Vegas NV, US
Rob Wouter Lohman - Dana Point CA, US
Richard Greene - Austin TX, US

Assignee:

Red.com, Inc. - Irvine CA

International Classification:

G06T 9/00
G06T 9/005
H04N 7/26
G06T 1/60

US Classification:

382166, 382234, 382240, 382244, 382248, 345530, 345555, 3483981

Abstract:

The disclosure herein relates to devices for compression, decompression or reconstruction of image data for still or moving pictures, such as image data detected with a digital camera. In some embodiments, data channels are compressed using a scalable compression algorithm. The compression algorithm may allow customization of compression parameters, such as a quantization factor, code block size, number of transform levels, reversible or irreversible compression, a desired compression ratio with a variable bit rate output, a desired fixed bit rate output with a variable compression rate, progression order, output format, or visual weighting. A lower quality image or an image with lower resolution may be reconstructed using only some of the compressed data. Use of offsets to various layers and color channels allow reconstruction of the image without requiring decompression of all of the full image data.

US Patent:

20100095114, Apr 15, 2010

Filed:

Oct 10, 2008

Appl. No.:

12/249305

Inventors:

Richard Greene - Austin TX, US
Igor Komir - Austin TX, US
Ronnin Yee - Round Rock TX, US

International Classification:

H04L 9/18
H04L 29/06

US Classification:

713160, 380 42

Abstract:

A method of encrypting a data stream includes receiving the data stream, and for each data packet in the data stream, forming an encrypted packet by encrypting a header portion of the data packet while leaving a body portion of the data packet unencrypted. The method also includes assembling an encrypted data stream comprising all the encrypted packets, and outputting the encrypted data stream.

US Patent:

53271335, Jul 5, 1994

Filed:

Feb 16, 1993

Appl. No.:

8/019379

Inventors:

Richard L. Greene - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03M 150

US Classification:

341143

Abstract:

A digital integrator (22) reduces circuit area and power consumption by implementing a two-stage integration for a decimator with only one adder (51). In the z-domain, he transfer function of a two-stage integrator can be expressed as H(z)=(1/(1-z. sup. -1)). sup. 2. Expanded, the transfer function is expressed as H(z)=(1/(1 -2z. sup. -1 +z. sup. -2)). The inverse z-transform yields the expression y[n]=x[n]+2y[n-1]-y[n-2], which can be implemented with a single adder (51) and two delay portions (52, 55 and 53, 54). In one embodiment, a three-stage integrator (22) can further be implemented within a single adder circuit (91) by time-multiplexing an addition required for the two-stage integration with an addition required for a one-stage integration inside the adder circuit (91).

US Patent:

59845147, Nov 16, 1999

Filed:

Dec 20, 1996

Appl. No.:

8/770518

Inventors:

Richard Greene - Austin TX
Mark Rossman - Austin TX
Phil Hallmark - Austin TX

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 1700

US Classification:

36471502

Abstract:

A video compression circuit comprises an input that receives an input video signal. A memory buffer, coupled to the input, temporarily stores a portion of the input video signal. A single horizontal filter bank, coupled to the memory buffer, high-pass and low-pass filters horizontal components of the input video signal. A single vertical filter bank, also coupled to the memory buffer, high-pass and low-pass filters vertical components of the input video signal. A recursion buffer, coupled to the filter banks, temporarily stores filter components of the input video signal for recursive filtering.

US Patent:

56529031, Jul 29, 1997

Filed:

Nov 1, 1994

Appl. No.:

8/332971

Inventors:

Walter U. Kuenast - Austin TX
Donald C. Anderson - Austin TX
Peter C. Curtis - Austin TX
Richard L. Greene - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 900

US Classification:

395800

Abstract:

A DSP co-processor (72) that is used on an integrated circuit (24) that provides multiple communication functions is accomplished by providing a data bus interface (320), a sequencer (328), internal memory (33), and a data core (322). The sequencer (328) stores in a hardware format a signal processing algorithm (332) and, upon receipt of an operational command, provides address control signals (334) and operation control signals (336) to the data core (322). The data core (322), which includes an address generation unit (340) and an arithmetic unit (344), executes, via the arithmetic unit, operational instructions of the signal processing algorithm to produce resultant signals from the input samples, the intermediate resultants, and the algorithm co-efficients.

US Patent:

58383778, Nov 17, 1998

Filed:

Dec 20, 1996

Appl. No.:

8/777705

Inventors:

Richard Greene - Austin TX

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04N 730

US Classification:

348398

Abstract:

A video compression circuit comprises an input that receives an input video signal. A memory buffer, coupled to the input, temporarily stores a portion of the input video signal. A single horizontal filter bank, coupled to the memory buffer, high-pass and low-pass filters horizontal components of the input video signal. A single vertical filter bank, also coupled to the memory buffer, high-pass and low-pass filters vertical components of the input video signal. A recursion buffer, coupled to the filter banks, temporarily stores filter components of the input video signal for recursive filtering.

US Patent:

20180070061, Mar 8, 2018

Filed:

Jul 21, 2017

Appl. No.:

15/656958

Inventors:

- Irvine CA, US
Thomas Graeme Nattress - Acton, CA
Richard Greene - Austin TX, US
Uday Mathur - Los Angeles CA, US

International Classification:

H04N 9/04
H04N 5/232
H04N 9/64
H04N 19/426
H04N 19/44
H04N 5/225

Abstract:

Embodiments provide a video camera that can be configured to highly compress video data in a visually lossless manner. The camera can be configured to transform blue, red, and/or green image data in a manner that enhances the compressibility of the data. The camera can be configured to transform at least a portion of the green image data in a manner that enhances the compressibility of the data. The data can then be compressed and stored in this form. This allows a user to reconstruct the red, blue, and/or green image data to obtain the original raw data or a modified version of the original raw data that is visually lossless when demosaiced. Additionally, the data can be processed in a manner in which at least some of the green image elements are demosaiced first and then the red, blue, and/or some green elements are reconstructed based on values of the demosaiced green image elements.

Address:

39 Chad Ct, Coralville, IA 52241

VIN:

5N1AN08W87C547357

Make:

NISSAN

Model:

XTERRA

Year:

2007