Naked Labs Jan 2018 - Apr 2019
Senior Vice President
Doppler Labs 2017 - 2017
Chief Technology Officer
Amazon Lab126 2013 - 2015
Vice President Hardware
Ddt Software 2011 - 2012
Chief Executive Officer
Sandisk 2008 - 2010
Senior Vice President and General Manager
Education:
Washington University In St. Louis
Master of Science, Masters, Computer Science
Washington University In St. Louis
Bachelors, Bachelor of Science, Computer Science, Electronics Engineering
Skills:
Semiconductors Product Management Strategic Partnerships Cross Functional Team Leadership Embedded Systems Soc Software Development Asic Start Ups Product Development Product Marketing Go To Market Strategy Ic Program Management Debugging Engineering Management Strategy Management Strategic Planning System Architecture Competitive Analysis Consumer Electronics Hardware Architecture Mobile Devices Business Development Cloud Computing Enterprise Software Semiconductor Industry Testing Wireless System on A Chip Analog Business Alliances Business Strategy Computer Architecture Embedded Software Eda Executive Management Hardware Mobile Applications Multi Channel Marketing Perl Product Launch Product Lifecycle Management Saas Software Engineering Storage Team Leadership Verilog Mergers
Us Patents
Nand Flash Memory Controller Exporting A Nand Interface
Eliyahou Harari - Saratoga CA, US Richard R. Heye - Sunnyvale CA, US Robert D. Selinger - San Jose CA, US Menahem Lasser - Kohav-Yair, IL
Assignee:
SanDisk IL Ltd. - Kfar Saba
International Classification:
G11C 29/00
US Classification:
714763, 36518509, 36518533
Abstract:
A NAND controller for interfacing between a host device and a flash memory device (e. g. , a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e. g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e. g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed.
Controller And Method For Interfacing Between A Host Controller In A Host And A Flash Memory Device
Eliyahou Harari - Saratoga CA, US Richard R. Heye - Sunnyvale CA, US Robert D. Selinger - San Jose CA, US
International Classification:
G06F 12/02 H03M 13/05 G06F 11/10 G06F 12/14
US Classification:
714773, 711103, 713193, 711E12008, 714E11032
Abstract:
The embodiments described herein provide a controller and method for interfacing between a host controller in a host and a flash memory device. In one embodiment, a controller comprises a first NAND interface, a second NAND interface, and one or more of the following modules: a data scrambling module, a column replacement module, and a module that manages at least one of bad blocks and spare blocks. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.
Nand Flash Memory Controller Exporting A Nand Interface
Eliyahou Harari - Saratoga CA, US Richard R. Heye - Sunnyvale CA, US Robert D. Selinger - San Jose CA, US Menahem Lasser - Kohav-Yair, IL
International Classification:
G06F 12/02
US Classification:
711103
Abstract:
A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.
Pipeline Utilizing An Integral Cache For Transferring Data To And From A Register
Richard T. Witek - Littleton MA Douglas D. Williams - Pepperell MA Timothy J. Stanley - Leominster MA David M. Fenwick - Chelmsford MA Douglas J. Burns - Billerica MA Rebecca L. Stamm - Newton MA Richard Heye - Somerville MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 1208
US Classification:
395800
Abstract:
A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.
Pipeline Having An Integral Cache Which Processes Cache Misses And Loads Data In Parallel
Richard T. Witek - Littleton MA Douglas D. Williams - Pepperell MA Timothy J. Stanley - Leominster MA David M. Fenwick - Chelmsford MA Douglas J. Burns - Billerica MA Rebecca L. Stamm - Newton MA Richard Heye - Somerville MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 938
US Classification:
395425
Abstract:
A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.
Method And Apparatus For Testing Processor-Based Computer Modules
William H. Cummins - Tewksbury MA R. Stephen Polzin - Morgan Hill CA Richard Heye - Sunnyvale CA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 1122
US Classification:
364580
Abstract:
A method and apparatus for testing complex processor-based computer modules and their associated computer systems by allowing the normal initialization path between a memory component storing code utilized during initialization and the processor to be interrupted and test code from an external test system to be substituted for initialization code. Following initialization, a two-way communication link between the processor and the test system is created to allow interactive testing and status reporting. The testing method and apparatus maximizes the likelihood of precisely identifying defects on the module under test.
Controller And Method For Interfacing Between A Host Controller In A Host And A Flash Memory Device
- Plano TX, US Richard R. Heye - Sunnyvale CA, US Robert D. Selinger - San Jose CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
G06F 11/10 G11C 29/00 G06F 12/02
US Classification:
714773, 711103
Abstract:
The embodiments described herein provide a controller and method for interfacing between a host controller in a host and a flash memory device. In one embodiment, a controller comprises a first NAND interface, a second NAND interface, and one or more of the following modules: a data scrambling module, a column replacement module, and a module that manages at least one of had blocks and spare blocks. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.
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