A method for preparing a sample includes separating a portion of substrate from a sample, performing focused ion beam milling, and removing additional sample material using an etchant.
Richard B. Irwin - Richardson TX, US Tony T. Phan - Flower Mound TX, US Jennifer S. Dumin - Wylie TX, US Patrick J. Jones - Allen TX, US Fredric D. Bailey - Irving TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L027/95
US Classification:
257478, 257473
Abstract:
An embodiment of the invention is a Schottky diode having a semiconductor substrate , a first metal , a barrier layer , and second metal. Another embodiment of the invention is a method of manufacturing a Schottky diode that includes providing a semiconductor substrate , forming a barrier layer over the semiconductor substrate , forming a first metal layer over the semiconductor substrate , annealing the semiconductor substrate to form areas of reacted first metal and areas of un-reacted first metal, and removing selected areas of the un-reacted first metal. The method further includes forming a second metal layer over the semiconductor substrate and annealing the semiconductor substrate to form areas of reacted second metal and areas of un-reacted second metal.
Method For Reducing Dislocation Threading Using A Suppression Implant
Martin Mollat - McKinney TX, US Tathagata Chatterjee - Allen TX, US Henry L. Edwards - Garland TX, US Lance S. Robertson - Rockwall TX, US Richard B. Irwin - Richardson TX, US Binghua Hu - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 29/93 H01L 23/62
US Classification:
257577, 257E21608, 257260, 257360
Abstract:
The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.
Method For Reducing Dislocation Threading Using A Suppression Implant
Martin Mollat - McKinney TX, US Tathagata Chatterjee - Allen TX, US Henry L. Edwards - Garland TX, US Lance S. Robertson - Rockwall TX, US Richard B. Irwin - Richardson TX, US Binghua Hu - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/28 H01L 21/44
US Classification:
438570, 438571, 438573, 257E21608
Abstract:
The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well () within a substrate () and forming a suppression implant () within the substrate (). The method for manufacturing the zener diode may further include forming a cathode () and an anode () within the substrate (), wherein the suppression implant () is located proximate the doped well () and configured to reduce threading dislocations.
Method Of Manufacturing A Dual Metal Schottky Diode
Richard B. Irwin - Richardson TX, US Tony T. Phan - Flower Mound TX, US Jennifer S. Dumin - Wylie TX, US Patrick J. Jones - Allen TX, US Fredric D. Bailey - Irving TX, US
An embodiment of the invention is a Schottky diode having a semiconductor substrate , a first metal , a barrier layer , and second metal. Another embodiment of the invention is a method of manufacturing a Schottky diode that includes providing a semiconductor substrate , forming a barrier layer over the semiconductor substrate , forming a first metal layer over the semiconductor substrate , annealing the semiconductor substrate to form areas of reacted first metal and areas of un-reacted first metal, and removing selected areas of the un-reacted first metal. The method further includes forming a second metal layer over the semiconductor substrate and annealing the semiconductor substrate to form areas of reacted second metal and areas of un-reacted second metal.
Dummy-Fill-Structure Placement For Improved Device Feature Location And Access For Integrated Circuit Failure Analysis
Jeffrey Large - Dallas TX, US Tathagata Chatterjee - Allen TX, US Richard Irwin - Richardson TX, US
Assignee:
Texas Instruments Inc. - Dallas TX
International Classification:
H01L 23/544 H01L 21/4763
US Classification:
257758000, 257797000, 438622000, 438401000
Abstract:
An integrated circuit comprising interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The dummy-fill-structures form a plurality of fiducials, each of the fiducials being located in a different region of the layer. Each fiducial comprises a pre-defined recognition pattern that is different from every other fiducial in adjacent regions of the layer.
Structure And Method For Coupling Heat To An Embedded Thermoelectric Device
Richard B. Irwin - Richardson TX, US Tathagata Chatterjee - Allen TX, US
International Classification:
H01L 35/30 H01L 35/34
US Classification:
136207, 438 54, 136201
Abstract:
An integrated circuit with an embedded heat exchanger for coupling heat to an embedded thermoelectric device from a thermal source that is electrically isolated from a thermoelectric device. A method for forming an integrated circuit with an embedded heat exchanger.
License Records
Richard W Irwin
License #:
1553 - Active
Category:
Electricians
Issued Date:
Apr 5, 1976
Expiration Date:
May 31, 2018
Type:
Electrician Master
Richard W Irwin
License #:
1553 - Active
Category:
Electricians
Issued Date:
Apr 5, 1976
Expiration Date:
May 31, 2018
Type:
Electrician Master
Resumes
Data Analytics, Failure Analysis, And Material Charaterization Engineer
Statistical Analysis and Strategy Manager at Hewlett-Packard, Adjunct Professor of Material Science and Engineering at University of Texas at Dallas
Location:
Dallas/Fort Worth Area
Industry:
Semiconductors
Work:
Hewlett-Packard - Plano, TX since Jun 2013
Statistical Analysis and Strategy Manager
University of Texas at Dallas - Dallas/Fort Worth Area since 2004
Adjunct Professor of Material Science and Engineering
Texas Instruments - Dallas/Fort Worth Area Nov 2001 - Apr 2013
Senior Member of the Technical Staff
University of Central Florida - Orlando, Florida Area 1997 - 2001
Adjunct Professor of Mechanical Engineering
AT&T/Lucent/Agere - Orlando, Florida Area 1994 - 2001
Member of the Technical Staff
Education:
University of Pittsburgh 1980 - 1984
Doctor of Philosophy (Ph.D.), Physics
University of Pittsburgh 1979 - 1980
Master of Science (M.S.), Physics
University of Pittsburgh 1975 - 1979
Bachelor of Science (B.S.), Honors Physics, Mathematics, and Computer Science (triple major)
Interests:
Material Science, Failure Analysis, Innovations, Data Analysis, Materials Characterization, Testing, Mentoring, Teaching, Servant Leadership, Out-of-the-Box Thinking, Continuous Improvement, Quality, Statistics
Dr. Irwin graduated from the Tufts University School of Medicine in 1968. He works in Worcester, MA and specializes in Pulmonary Critical Care Medicine. Dr. Irwin is affiliated with UMASS Memorial Medical Center.