Richard T Mackey

US Patent:

6460108, Oct 1, 2002

Filed:

Mar 31, 1999

Appl. No.:

09/282386

Inventors:

Jeff J. McCoskey - Phoenix AZ
Richard P. Mackey - Phoenix AZ
Barry R. Davis - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710310, 710 57, 710305, 710306, 710307

Abstract:

A method and apparatus for providing an efficient, low cost data streaming mechanism from a first bus architecture to a second bus architecture across a bus bridge. Separate read and write data queues are provided in the bus bridge for transfer of data in both directions, and the speed of one of the buses is increased over the speed of the other one of the buses. In one embodiment, the first bus is a PCI bus and the second bus is an internal CPU bus.

US Patent:

7000146, Feb 14, 2006

Filed:

May 31, 2001

Appl. No.:

09/872872

Inventors:

Richard P. Mackey - Phoenix AZ, US
Richard P. Luckett - Phoenix AZ, US
James D. Warren - Chandler AZ, US
Sailesh Bissessur - Gilbert AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 22, 714 24, 714 27, 713340

Abstract:

A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

US Patent:

7080187, Jul 18, 2006

Filed:

Dec 20, 2001

Appl. No.:

10/028881

Inventors:

Richard P. Mackey - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00
G06F 13/28
G06F 13/36

US Classification:

710306, 710 26, 710101, 710 4

Abstract:

Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus enviroment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a data bus address. A decoder may provide bus segment information to the bridge independently of a bus transaction on the second data bus initiated by a source device. The bridge may comprise logic to forward the bus transaction on the first data bus to the target device based upon the bus segment information.

US Patent:

7123674, Oct 17, 2006

Filed:

May 31, 2001

Appl. No.:

09/872277

Inventors:

Richard P. Mackey - Phoenix AZ, US
David R. Smith - Phoenix AZ, US
Jeffrey J. McCoskey - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 7/00

US Classification:

375354, 375371

Abstract:

Reducing latency and power in the transfer of data between a source and destination domain involves the production of a source-enable signal base on a synchronous-pulse signal. The source-enable signal operates to enable a source register to capture data from a source domain. The source-enable signal may be controlled by a source-inhibit signal. The source-inhibit signal prevents the synchronous-pulse signal from producing the source enable signal and capture clock until data is available for transmission.

US Patent:

7124230, Oct 17, 2006

Filed:

Apr 30, 2002

Appl. No.:

10/136660

Inventors:

David Russell Smith - Phoenix AZ, US
Richard Paul Mackey - Phoenix AZ, US
Joseph Murray - Scottsdale AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/36
G06F 13/372
G06F 13/00

US Classification:

710310, 710306, 710129, 710301

Abstract:

A peripheral component interconnect-extended system that includes a bus bridge. The bus bridge includes an input queue adapted to receive a first request for data from a requesting device coupled to a first bus. The first bus is coupled to the bus bridge, and the first request containing a sequence identification information. The bus bridge also includes a data storage device to contain information to control the bus bridge, and a processor that associates a first unique identification code to the first request.

US Patent:

7130933, Oct 31, 2006

Filed:

Jul 24, 2002

Appl. No.:

10/205663

Inventors:

Sailesh Bissessur - Phoenix AZ, US
Richard P. Mackey - Phoenix AZ, US
Mark A. Schmisseur - Phoenix AZ, US
David R. Smith - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/28

US Classification:

710 22, 710 23, 710 24, 710 25, 710 26, 710 27, 710 28

Abstract:

Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.

US Patent:

7290127, Oct 30, 2007

Filed:

Dec 26, 2001

Appl. No.:

10/032762

Inventors:

Mark A Schmisseur - Phoenix AZ, US
Timothy J Jehl - Higley AZ, US
Richard P Mackey - Phoenix AZ, US
Delf Atallah - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/177

US Classification:

713 2, 709204, 710311, 710 22, 713 1, 713310

Abstract:

A system and method of initializing a core processing circuit are disclosed. The core processing circuit is held in a reset state while a reset vector is loaded to one or more registers at a boot address associated with the core processing circuit. The reset vector is loaded from a system memory through a host bridge. The reset vector comprises one or more instructions to initialize the core processing system upon release from a reset state.

US Patent:

7464199, Dec 9, 2008

Filed:

Apr 7, 2006

Appl. No.:

11/279086

Inventors:

Sailesh Bissessur - Phoenix AZ, US
Richard P. Mackey - Phoenix AZ, US
Mark A. Schmisseur - Phoenix AZ, US
David R. Smith - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/28

US Classification:

710 22, 710 23, 710 26, 710 27, 710 28

Abstract:

Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.