Richard O Mann

US Patent:

6486522, Nov 26, 2002

Filed:

Sep 28, 1999

Appl. No.:

09/407741

Inventors:

Magued Bishay - Costa Mesa CA
Randall M. Chung - Laguna Niguel CA
James K. Dawson - Huntington Beach CA
David Escobar - San Juan Capistrano CA
Mike Fukatsu - La Mirada CA
Edward Andrew Jakl - Tustin CA
Richard Arthur Mann - Torrance CA
Sarit Neter - Irvine CA
Ian Olsen - Irvine CA
Gregory A. Urban - Las Flores CA

Assignee:

Pictos Technologies, Inc. - Newport Beach CA

International Classification:

H01L 3100

US Classification:

257444, 257431

Abstract:

The invention is an imaging device having a high fill factor. The high fill factor is achieved by constructing the light sensors in a vertical fashion in the imaging device. The control circuitry of the light sensor is then contained inside the integrated circuit chip, rather than taking up area that could otherwise be used for light collection. The majority of the area on the surface of the IC chip is made up of light sensing elements, since the control circuitry is embedded in the IC chip. The control circuitry is connected to the light sensing devices through vias in the IC chip. The control circuitry of the chip is mainly contained within the die, rather than on it.

US Patent:

6838715, Jan 4, 2005

Filed:

Apr 29, 2003

Appl. No.:

10/425488

Inventors:

Selim Bencuya - Irvine CA, US
Richard Mann - Torrance CA, US
Erik Stauber - San Diego CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H01L 31062

US Classification:

257291, 257184, 257187, 257203, 257292, 257293, 257433, 257461, 257462, 257929

Abstract:

An exemplary CMOS image sensor comprises a plurality of pixels arranged in an array. The plurality of pixels includes a first pixel proximate an optical center of the array, and a second pixel proximate a peripheral edge of the array. The CMOS image sensor further comprises a first metal interconnect segment associated with the first pixel situated in a first metal layer, and a second metal interconnect segment associated with the second pixel situated in the first metal layer. The second metal interconnect segment is shifted closer to the optical center of the array than the first metal interconnect segment so that the second metal interconnect segment approximately aligns with a principle ray angle incident the second pixel, thereby reducing pixel light shadowing.

US Patent:

6911640, Jun 28, 2005

Filed:

Apr 25, 2003

Appl. No.:

10/423681

Inventors:

Selim Bencuya - Irvine CA, US
Richard Mann - Torrance CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H04N003/14

US Classification:

2502081, 348308

Abstract:

An exemplary CMOS image sensor comprises a reset transistor, a photodiode, reset drain voltage circuitry, and reset gate voltage circuitry. A cathode of the photodiode is connected to a source of the reset transistor, and an anode of the photodiode is connected to ground. The reset drain voltage circuitry is connected to a drain of the reset transistor, and the reset gate voltage circuitry is connected to a gate of the reset transistor. During an exemplary hard reset operation, the reset drain voltage circuitry supplies a first drain voltage to the drain of the reset transistor in accordance with a determined level of light for exposure, which is determined dynamically. According to another exemplary reset operation, a hard reset phase is immediately followed by a soft reset phase.

US Patent:

7067786, Jun 27, 2006

Filed:

Mar 17, 2005

Appl. No.:

11/083466

Inventors:

Selim Bencuya - Irvine CA, US
Richard Mann - Torrance CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H04N 3/14
H04N 5/335

US Classification:

2502081, 348308

Abstract:

An exemplary CMOS image sensor comprises a reset transistor, a photodiode, reset drain voltage circuitry, and reset gate voltage circuitry. A cathode of the photodiode is connected to a source of the reset transistor, and an anode of the photodiode is connected to ground. The reset drain voltage circuitry is connected to a drain of the reset transistor, and the reset gate voltage circuitry is connected to a gate of the reset transistor. During an exemplary hard reset operation, the reset drain voltage circuitry supplies a first drain voltage to the drain of the reset transistor in accordance with a determined level of light for exposure, which is determined dynamically. According to another exemplary reset operation, a hard reset phase is immediately followed by a soft reset phase.

US Patent:

7323671, Jan 29, 2008

Filed:

Dec 30, 2004

Appl. No.:

11/029103

Inventors:

Zeynep Toros - Aliso Viejo CA, US
Richard Mann - Torrance CA, US
Selim Bencuya - Irvine CA, US
Chi-Shao (Sergi) Lin - Mission Viejo CA, US
Jiafu Luo - Irvine CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H01L 27/00
G01J 1/44
H03F 3/08
H01J 40/14

US Classification:

2502081, 250214 R, 257291, 348302

Abstract:

An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

US Patent:

7334211, Feb 19, 2008

Filed:

Dec 30, 2004

Appl. No.:

11/029101

Inventors:

Zeynep Toros - Aliso Viejo CA, US
Richard Mann - Torrance CA, US
Selim Bencuya - Irvine CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

G06F 17/50

US Classification:

716 19, 716 11, 716 21

Abstract:

An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

US Patent:

7385272, Jun 10, 2008

Filed:

Mar 2, 2007

Appl. No.:

11/713822

Inventors:

Zeynep Toros - Aliso Viejo CA, US
Richard Mann - Torrance CA, US
Selim Bencuya - Irvine CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H01L 31/06

US Classification:

257463, 257462, 257464, 257465, 257E31073, 257E27139, 438 79

Abstract:

An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

US Patent:

7495274, Feb 24, 2009

Filed:

Dec 30, 2004

Appl. No.:

11/026278

Inventors:

Zeynep Toros - Aliso Viejo CA, US
Richard Mann - Torrance CA, US
Selim Bencuya - Irvine CA, US

Assignee:

ESS Technology, Inc. - Fremont CA

International Classification:

H01L 27/146

US Classification:

257292, 257E27133

Abstract:

An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.