Richard A Marshall

US Patent:

20100262755, Oct 14, 2010

Filed:

Apr 10, 2009

Appl. No.:

12/421848

Inventors:

Eric Becker - Peoria AZ, US
Rick Carmichael - Phoenix AZ, US
Brian Keller - Glendale AZ, US
Vince J. Gavagan - Peoria AZ, US
William A. Fiedler - St. Petersburg FL, US
Richard Marshall - Glendale AZ, US

Assignee:

HONEYWELL INTERNATIONAL INC. - Morristown NJ

International Classification:

G06F 12/00
G06F 12/02

US Classification:

711103, 711114, 714777, 36518509, 711E12001, 711E12008

Abstract:

Memory systems and devices are provided. One memory system includes a controller configured to be coupled to a plurality of computing devices, a plurality of Multi-Level Cell (MLC) devices coupled to the controller, and a Single-Level Cell (SLC) device coupled to the controller and the plurality of MLC devices. The MLC devices are configured to split the storage of data across the plurality of MLC devices and the SLC device is configured to function as a parity device for the data. A memory device includes a controller, a plurality of MLC FLASH devices, and a SLC FLASH device. The MLC FLASH devices are configured to split the storage of data across the plurality of MLC FLASH devices and the SLC FLASH device is configured to function as a parity device for the data. Also provided are computing devices including the above memory device.

US Patent:

20210376598, Dec 2, 2021

Filed:

Aug 6, 2021

Appl. No.:

17/395658

Inventors:

- Charlotte NC, US
Richard L. Marshall - Glendale AZ, US

Assignee:

HONEYWELL INTERNATIONAL INC. - Charlotte NC

International Classification:

H02H 9/02
H02H 3/093
H02H 1/00

Abstract:

Embodiments of a single event latch-up (SEL) protection circuit are provided, including: a first circuitry block coupled to a source of an input voltage a load, and digitally controlling a first switch; the first switch generates a load and senses an instantaneous load current iLoad. A second circuitry block is configured to generate an average iLoad and generate single event latch-up triggers (i.e., SEL fault detection) as a function of at least a comparison of the inst_iLoad and average iLoad; wherein this first circuitry block contains the analog based SET filtering needed to reduce false SEL triggers. A supervisor module generates on/off commands for the first switch, responsive to receiving the SEL detection in excess of a pre-programmed delay to provide the final SET filtering to prevent false SEL triggers. The first circuitry block removes the load voltage at N upon receiving an off command from the supervisor module.

US Patent:

20200266622, Aug 20, 2020

Filed:

Feb 19, 2019

Appl. No.:

16/279580

Inventors:

- Morris Plains NJ, US
Richard L. Marshall - Glendale AZ, US

Assignee:

HONEYWELL INTERNATIONAL INC. - Morris Plains NJ

International Classification:

H02H 9/02
H03K 19/003

Abstract:

Embodiments of a single event latch-up (SEL) protection circuit are provided, including: a first circuitry block coupled to a source of an input voltage a load, and digitally controlling a first switch; the first switch generates a load and senses an instantaneous load current iLoad. A second circuitry block is configured to generate an average iLoad and generate single event latch-up triggers (i.e., SEL fault detection) as a function of at least a comparison of the inst_iLoad and average iLoad; wherein this first circuitry block contains the analog based SET filtering needed to reduce false SEL triggers. A supervisor module generates on/off commands for the first switch, responsive to receiving the SEL detection in excess of a preprogrammed delay to provide the final SET filtering to prevent false SEL triggers. The first circuitry block removes the load voltage at N upon receiving an off command from the supervisor module.